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fix comparaisons between var and float
1 parent e16bea6 commit bc97b8e

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2 files changed

+20
-0
lines changed

2 files changed

+20
-0
lines changed

winxedst1.winxed

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3970,6 +3970,16 @@ class ComparatorBaseExpr : OpBinaryExpr
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e.emitset(aux, regr);
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regr = aux;
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break;
3973+
case rr == REGfloat && rl == REGvar:
3974+
aux = self.tempreg(REGfloat);
3975+
e.emitset( aux, regl);
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regl = aux;
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break;
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case rr == REGvar && rl == REGfloat:
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aux = self.tempreg(REGfloat);
3980+
e.emitset(aux, regr);
3981+
regr = aux;
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break;
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case rr == REGstring && rl == REGvar:
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aux = self.tempreg(REGstring);
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e.emitset(aux, regl);

winxedst2.winxed

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4961,6 +4961,16 @@ class ComparatorBaseExpr : OpBinaryExpr, ConditionFriendlyExpr
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e.emitset(aux, regr);
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regr = aux;
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break;
4964+
case rr == REGfloat && rl == REGvar:
4965+
aux = self.tempreg(REGfloat);
4966+
e.emitset( aux, regl);
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regl = aux;
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break;
4969+
case rr == REGvar && rl == REGfloat:
4970+
aux = self.tempreg(REGfloat);
4971+
e.emitset(aux, regr);
4972+
regr = aux;
4973+
break;
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case rr == REGstring && rl == REGvar:
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aux = self.tempreg(REGstring);
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e.emitset(aux, regl);

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