reset detection for issue#14

[fukatani]

Implemented reset detection method for #14
Reset is not detected if always block doesn't have 'if branch', or substitute variable at first branch, or first if condition is too complex.
In other case reset is get from first if condition.

In case of multiple bind in one always block, if reset is sync reset, permitted 'mix' signals with/without signals reset.

//OK! RST is reset for reg1, but not influence on reg2.
  always @(posedge CLK ) begin
    if(RST) begin
      reg1 <= 8'd0;
    end else begin
      reg1 <= 8'd0;
      reg2 <= 8'd1;
    end
  end

If reset is asyncronus, raised exception. (Illegal RTL.)

  //Illegal! RST is regard as clock signal for reg2 by verilog simulator.
  always @(posedge CLK or posedge RST) begin
    if(RST) begin
      reg1 <= 8'd0;
    end else begin
      reg1 <= 8'd0;
      reg2 <= 8'd1;
    end
  end