modify for $signed and $unsigned

pyverilog/dataflow/dataflow.py

@@ -1,9 +1,10 @@
 #-------------------------------------------------------------------------------
 # dataflow.py
-# 
+#
 # Basic classes of Data flow nodes
 #
 # Copyright (C) 2013, Shinya Takamaeda-Yamazaki
+# modified by ryoduke fukatani
 # License: Apache 2.0
 #-------------------------------------------------------------------------------
 
@@ -47,7 +48,7 @@ def __repr__(self): pass
     def tostr(self): pass
     def tocode(self, dest='dest'): return self.__repr__()
     def tolabel(self): return self.__repr__()
-    def children(self): 
+    def children(self):
         nodelist = []
         return tuple(nodelist)
     def __eq__(self, other):
@@ -69,8 +70,8 @@ def __repr__(self):
         return ret[:-1]
     def tostr(self):
         ret = '(Terminal '
-        for n in self.name:      
-            ret += str(n) + '.'            
+        for n in self.name:
+            ret += str(n) + '.'
         return ret[0:-1] + ')'
     def tocode(self, dest='dest'):
         #ret = ''
@@ -207,7 +208,7 @@ def __eq__(self, other):
         return self.operator == other.operator and self.nextnodes == other.nextnodes
     def __hash__(self):
         return hash((self.operator, tuple(self.nextnodes)))
-    
+
 class DFPartselect(DFNotTerminal):
     attr_names = ()
     def __init__(self, var, msb, lsb):
@@ -312,8 +313,8 @@ def __repr__(self):
         return 'Branch'
     def tostr(self):
         ret = '(Branch'
-        if self.condnode is not None: ret += ' Cond:' + self.condnode.tostr() 
-        if self.truenode is not None: ret += ' True:' + self.truenode.tostr() 
+        if self.condnode is not None: ret += ' Cond:' + self.condnode.tostr()
+        if self.truenode is not None: ret += ' True:' + self.truenode.tostr()
         if self.falsenode is not None: ret += ' False:'+ self.falsenode.tostr()
         ret += ')'
         return ret
@@ -334,15 +335,15 @@ def _tocode_always(self, dest='dest', always='clockedge'):
         ret = 'if('
         if self.condnode is not None: ret += self.condnode.tocode(dest)
         ret += ') begin\n'
-        if self.truenode is not None: 
+        if self.truenode is not None:
             if isinstance(self.truenode, DFBranch):
                 ret += self.truenode.tocode(dest, always=always)
             elif always == 'clockedge':
                 ret += dest + ' <= ' + self.truenode.tocode(dest) + ';\n'
             elif always == 'combination':
                 ret += dest + ' = ' + self.truenode.tocode(dest) + ';\n'
         ret += 'end\n'
-        if self.falsenode is not None: 
+        if self.falsenode is not None:
             ret += 'else begin\n'
             if isinstance(self.falsenode, DFBranch):
                 ret += self.falsenode.tocode(dest, always=always)
@@ -462,7 +463,7 @@ def __repr__(self):
         return 'Delay'
     def tostr(self):
         ret = '(Delay '
-        if self.nextnode is not None: ret += self.nextnode.tostr() 
+        if self.nextnode is not None: ret += self.nextnode.tostr()
         ret += ')'
         return ret
     def tocode(self, dest='dest'):
@@ -522,8 +523,8 @@ def __repr__(self):
         return str(self.name)
     def tostr(self):
         ret = '(Term name:' + str(self.name) + ' type:' + str(self.termtype)
-        if self.msb is not None: ret += ' msb:' + self.msb.tostr() 
-        if self.lsb is not None: ret += ' lsb:' + self.lsb.tostr() 
+        if self.msb is not None: ret += ' msb:' + self.msb.tostr()
+        if self.lsb is not None: ret += ' lsb:' + self.lsb.tostr()
         if self.lenmsb is not None: ret += ' lenmsb:' + self.lenmsb.tostr()
         if self.lenlsb is not None: ret += ' lenlsb:' + self.lenlsb.tostr()
         ret += ')'
@@ -641,7 +642,7 @@ def _localparam(self):
         code = 'localparam ' + dest
         code += ' = ' + self.tree.tocode(dest) + ';\n'
         return code
-            
+
     def _assign(self):
         dest = self.getdest()
         code = 'assign ' + dest
@@ -652,10 +653,10 @@ def _always_clockedge(self):
         dest = self.getdest()
         code = 'always @('
         if self.alwaysinfo.clock_edge is not None and self.alwaysinfo.clock_name is not None:
-            code += self.alwaysinfo.clock_edge + ' ' 
+            code += self.alwaysinfo.clock_edge + ' '
             code += util.toFlatname(self.alwaysinfo.clock_name)
         if self.alwaysinfo.reset_edge is not None and self.alwaysinfo.reset_name is not None:
-            code += ' or '            
+            code += ' or '
             code += self.alwaysinfo.reset_edge + ' '
             code += util.toFlatname(self.alwaysinfo.reset_name)
         code += ') begin\n'
@@ -681,7 +682,7 @@ def _always_combination(self):
         code += 'end\n'
         code += '\n'
         return code
-    
+
     def isClockEdge(self):
         if self.alwaysinfo is None: return False
         return self.alwaysinfo.isClockEdge()
@@ -752,7 +753,7 @@ def setBind(self, name, bind):
         currentbindlist = self.binddict[name]
         c_i = 0
         for c in currentbindlist:
-            if c.msb == bind.msb and c.msb == bind.msb and c.ptr == bind.ptr:
+            if c.msb == bind.msb and c.lsb == bind.lsb and c.ptr == bind.ptr:
                 self.binddict[name][c_i].tree = bind.tree
                 return
             c_i += 1

pyverilog/testcode/casex.v

@@ -0,0 +1,24 @@
+module TOP(CLK, RST, LED);
+  input CLK, RST;
+  output [7:0] LED;
+  reg [7:0] cnt;
+  always @(posedge CLK) begin
+    if(RST) begin
+      cnt <= 0;
+    end else begin
+      casex(cnt)
+        'b00: begin
+          cnt <= cnt + 1;
+        end
+        'b1x: begin
+          cnt <= 0;
+        end
+        default: begin
+          cnt <= cnt + 1;
+        end
+      endcase
+    end
+  end
+  assign LED = cnt;
+endmodule
+

pyverilog/testcode/signed.v

@@ -0,0 +1,18 @@
+//`default_nettype none
+
+module TOP(CLK, RST);
+  input CLK, RST;
+  reg [7:0] cnt;
+
+
+  always @(posedge CLK or negedge RST) begin
+    if(RST) begin
+      cnt <= 'd0;
+    end else begin
+      cnt <= cnt + 1'sd1;
+    end
+  end
+
+
+endmodule
+

pyverilog/testcode/signed_task.v

@@ -0,0 +1,14 @@
+module TOP(CLK, RST);
+  input CLK, RST;
+  reg [7:0] cnt;
+
+  always @(posedge CLK or negedge RST) begin
+    if(RST) begin
+      cnt <= $signed(cnt);
+    end else begin
+      cnt <= $unsigned(cnt);
+    end
+  end
+
+
+endmodule

pyverilog/testcode/test_sd.py

@@ -0,0 +1,113 @@
+#-------------------------------------------------------------------------------
+# test_sd.py
+#
+#
+#
+# Copyright (C) 2015, ryosuke fukatani
+# License: Apache 2.0
+#-------------------------------------------------------------------------------
+
+
+import sys
+import os
+import subprocess
+
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
+
+from pyverilog.dataflow.dataflow_analyzer import *
+import unittest
+
+
+class TestSequenceFunctions(unittest.TestCase):
+    def setUp(self):
+        path_clone = sys.path
+        pop_target = []
+        for i,path in enumerate(path_clone):
+            if path == 'C:\\Python27\\lib\\site-packages\\pyverilog-0.9.0-py2.7.egg':
+                pop_target.append(i)
+        for i in reversed(pop_target):
+            sys.path.pop(i)
+        reload(pyverilog.dataflow.dataflow_analyzer)
+
+    def test_signed(self):
+        terms, binddict = self.dataflow_wrapper("signed.v")
+        self.assertEqual(binddict.values()[0][0].tostr(),
+        "(Bind dest:TOP.cnt tree:(Branch Cond:(Terminal TOP.RST) True:(IntConst 'd0) False:(Operator Plus Next:(Terminal TOP.cnt),(IntConst 1'sd1))))")
+
+    def test_signed_task(self):
+        terms, binddict = self.dataflow_wrapper("signed_task.v")
+        self.assertEqual(binddict.values()[0][0].tostr(),
+        "(Bind dest:TOP.cnt tree:(Branch Cond:(Terminal TOP.RST) True:(Terminal TOP.cnt) False:(Terminal TOP.cnt)))")
+
+    def test_casex(self):
+        self.dataflow_wrapper("casex.v")
+
+    def dataflow_wrapper(self,code_file):
+
+        from optparse import OptionParser
+
+        optparser = OptionParser()
+        optparser.add_option("-v","--version",action="store_true",dest="showversion",
+                             default=False,help="Show the version")
+        optparser.add_option("-I","--include",dest="include",action="append",
+                             default=[],help="Include path")
+        optparser.add_option("-D",dest="define",action="append",
+                             default=[],help="Macro Definition")
+        optparser.add_option("-t","--top",dest="topmodule",
+                             default="TOP",help="Top module, Default=TOP")
+        optparser.add_option("--nobind",action="store_true",dest="nobind",
+                             default=False,help="No binding traversal, Default=False")
+        optparser.add_option("--noreorder",action="store_true",dest="noreorder",
+                             default=False,help="No reordering of binding dataflow, Default=False")
+
+        filelist = {code_file}
+        options = optparser.get_default_values()
+
+
+        for f in filelist:
+            if not os.path.exists(f): raise IOError("file not found: " + f)
+
+        verilogdataflowanalyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
+                                                          noreorder=options.noreorder,
+                                                          nobind=options.nobind,
+                                                          preprocess_include=options.include,
+                                                          preprocess_define=options.define)
+        verilogdataflowanalyzer.generate()
+
+        directives = verilogdataflowanalyzer.get_directives()
+        print('Directive:')
+        for dr in directives:
+            print(dr)
+
+        instances = verilogdataflowanalyzer.getInstances()
+        print('Instance:')
+        for ins in instances:
+            print(ins)
+
+        if options.nobind:
+            print('Signal:')
+            signals = verilogdataflowanalyzer.getSignals()
+            for sig in signals:
+                print(sig)
+
+            print('Const:')
+            consts = verilogdataflowanalyzer.getConsts()
+            for con in consts:
+                print(con)
+
+        else:
+            terms = verilogdataflowanalyzer.getTerms()
+            print('Term:')
+            for tk, tv in sorted(terms.items(), key=lambda x:len(x[0])):
+                print(tv.tostr())
+
+            binddict = verilogdataflowanalyzer.getBinddict()
+            print('Bind:')
+            for bk, bv in sorted(binddict.items(), key=lambda x:len(x[0])):
+                for bvi in bv:
+                    print(bvi.tostr())
+
+        return terms, binddict
+
+if __name__ == '__main__':
+    unittest.main()

pyverilog/vparser/ast.py

@@ -1,9 +1,10 @@
 #-------------------------------------------------------------------------------
 # ast.py
-# 
+#
 # Verilog HDL AST classes with Pyverilog
 #
 # Copyright (C) 2013, Shinya Takamaeda-Yamazaki
+# edited by ryosuke fukatani
 # License: Apache 2.0
 #-------------------------------------------------------------------------------
 
@@ -47,7 +48,7 @@ def __hash__(self):
         s = hash(tuple([getattr(self, a) for a in self.attr_names]))
         c = hash(self.children())
         return hash((s, c))
-        
+
 ################################################################################
 class Source(Node):
     attr_names = ('name',)
@@ -171,7 +172,7 @@ def children(self):
         nodelist = []
         if self.width: nodelist.append(self.width)
         return tuple(nodelist)
-        
+
 class Input(Variable): pass
 class Output(Variable): pass
 class Inout(Variable): pass
@@ -347,11 +348,11 @@ class Power(Operator): pass
 class Times(Operator): pass
 class Divide(Operator): pass
 class Mod(Operator): pass
-################################################################################    
+################################################################################
 # Level 3
 class Plus(Operator): pass
 class Minus(Operator): pass
-################################################################################    
+################################################################################
 # Level 4
 class Sll(Operator): pass
 class Srl(Operator): pass
@@ -510,6 +511,8 @@ def children(self):
         if self.caselist: nodelist.extend(self.caselist)
         return tuple(nodelist)
 
+class CasexStatement(CaseStatement): pass
+
 class Case(Node):
     attr_names = ()
     def __init__(self, cond, statement):
@@ -540,7 +543,7 @@ def children(self):
         if self.statement: nodelist.append(self.statement)
         return tuple(nodelist)
 
-class EventStatement(Node): 
+class EventStatement(Node):
     attr_names = ()
     def __init__(self, senslist):
         self.senslist = senslist
@@ -589,7 +592,7 @@ def children(self):
         if self.parameterlist: nodelist.extend(self.parameterlist)
         if self.instances: nodelist.extend(self.instances)
         return tuple(nodelist)
-    
+
 class Instance(Node):
     attr_names = ('name', 'module')
     def __init__(self, module, name, portlist, parameterlist, array=None):