RV-AT
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riscv-dv
riscv-dv PublicForked from chipsalliance/riscv-dv
SV/UVM based instruction generator for RISC-V processor verification
SystemVerilog 1
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Showing 10 of 23 repositories
- EveIDE_LIGHT Public Forked from Adancurusul/EveIDE_LIGHT
A lightweight IDE that supports verilog simulation and Risc-V code compilation
RV-AT/EveIDE_LIGHT’s past year of commit activity - 80x86 Public Forked from jamieiles/80x86
80186 compatible SystemVerilog CPU core and FPGA reference design
RV-AT/80x86’s past year of commit activity - SoC_Automation Public Forked from habibagamal/SoC_Automation
SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.
RV-AT/SoC_Automation’s past year of commit activity
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