target/cortex_m: fix soft_reset_halt

in GDB event "gdb-flash-erase-start", a soft reset dont perform correctly target need to halt
Unfortunately, the execution of soft reset fails with time out error
(after 100 ms: S_HALT not raised => Target not halted  => reset not performed).
After investigation, Accordingly to ARM DDI0403E.B, chapter “B3.2.6 Application Interrupt and Reset Control Register,
AIRCR” before setting DEMCR.VC_CORERESET to perform local system reset,
we must halt the core otherwisethe behavior is unpredictable.

Change-Id: I440c66dca5effa2079ae330a31e2311525539e29
Signed-off-by: fedi BOUZAZI <fedi.bouzazi@st.com>

Author: FBOSTM

src/target/cortex_m.c

@@ -1041,6 +1041,29 @@ static int cortex_m_soft_reset_halt(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 
+	/* Enter Debug state before setting 1 to AIRCR_VECTRESET */
+	retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
+	if (retval != ERROR_OK)
+		return retval;
+
+	/* Ensure core halted */
+	while (timeout < 100) {
+		retval = cortex_m_read_dhcsr_atomic_sticky(target);
+		if (retval == ERROR_OK) {
+			if (cortex_m->dcb_dhcsr & S_HALT) {
+				LOG_TARGET_DEBUG(target, "core halted, DHCSR 0x%08" PRIx32, cortex_m->dcb_dhcsr);
+				cortex_m_poll(target);
+				return ERROR_OK;
+			} else {
+					LOG_TARGET_DEBUG(target, "waiting for system reset-halt, "
+										"DHCSR 0x%08" PRIx32 ", %d ms",
+										cortex_m->dcb_dhcsr, timeout);
+			}
+		}
+		timeout++;
+		alive_sleep(1);
+	}
+
 	/* Enter debug state on reset; restore DEMCR in endreset_event() */
 	retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
 			TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
@@ -1057,6 +1080,9 @@ static int cortex_m_soft_reset_halt(struct target *target)
 	/* registers are now invalid */
 	register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
 
+	/* reset timeout to 0 */
+	timeout = 0;
+
 	while (timeout < 100) {
 		retval = cortex_m_read_dhcsr_atomic_sticky(target);
 		if (retval == ERROR_OK) {