Collection of digital logic design circuits implemented and simulated in Verilog HDL using Xilinx Vivado. This repository contains Verilog HDL implementations of fundamental digital logic design circuits, including adders, subtractors, multiplexers, encoders, decoders, and more. Each design is coded, simulated, and verified using Xilinx Vivado, demonstrating key combinational and sequential logic concepts used in VLSI design and digital systems.
The goal of this project is to strengthen understanding of digital logic and provide reusable, simulation-ready Verilog modules for students and enthusiasts exploring FPGA and ASIC design