Systemverilog_Concepts_and_Coding_by_Siba

Welcome to the SystemVerilog Coding repository, Systemverilog_Concepts_and_Coding_by_Siba !!!

Happy Learning & Coding 😄

This repository contains various SV Concepts with code examples that will help for functional verification engineers.

👯 Acknowledgments : System Verilog community members , Open Source resources and Verification experts who have helped a lot and guided me.

🤔 Encouragement : Don't forget to star this repository if you find it helpful throughout your learning !!!

⚡ GitHub Repo : https://github.com/Sibakumarpanda/Systemverilog_Concepts_and_Coding_by_Siba/

Running the Code

To run the UVM code examples in this repository, you can use EDA Playground, an online simulation platform. Follow these steps to get started:

Visit EDA Playground: Open your browser and go to EDA Playground.
Configure Your Environment:
- On the left side of the page, find the UVM option and set it to 1.1d or for some codes 1.2 .
- Set Tools & Simulators to any Simulation tools like Aldec/Synopsys/Cadence/Simens Questa. Here i have used mostly Synopsys VCS 2023.03.
Run the Simulation: After the configuration, simply click on the Run button to start the simulation.

The code will execute on the platform, and you can view the simulation results in the output section.

Content of this Repository

This repository contains the basic to advance level SV Concepts , code examples with complete understanding as per below Outline .

1. SV Data Types

2. SV Arrays- Fixed Size array , Single Dimension ,Multi Dimension array ,Packed/Unpacked array

3. Dynamic Array in SV

4. Associative Array in SV

5. Array Manipulation Methods

Array locator methods    
Array ordering methods    
Array reduction methods    
Iterator index querying

6. SV Queue overview and its various methods with examples

7. SV Structure overview and its various methods with examples

8. SV Union overview and its various methods with examples

9. Various if Statements in System Verilog with examples

 if
 else if /else 
 unique if
 unique0 if
 priority if

10. Looping Constructs in System Verilog with examples

 while loop
 do while loop
 forever loop
 for Loop
 foreach loop
 repeat loop
 break , continue

11. SV Function Concept with example

12. SV Task Concept with example

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Name		Name	Last commit message	Last commit date
Latest commit History 616 Commits
Full_case_Parallel_case_in_Verilog_Priority_Unique_in_System_verilog		Full_case_Parallel_case_in_Verilog_Priority_Unique_in_System_verilog
IPC_SV_Event_concepts_and_example		IPC_SV_Event_concepts_and_example
10_Looping_Constructs_in_SV_with_examples.sv		10_Looping_Constructs_in_SV_with_examples.sv
10_Looping_Constructs_more_examples_for_practice.sv		10_Looping_Constructs_more_examples_for_practice.sv
10_Looping_construct_do_while_flow_chart.jpg		10_Looping_construct_do_while_flow_chart.jpg
10_Looping_construct_for_loop_flow_chart.jpg		10_Looping_construct_for_loop_flow_chart.jpg
10_Looping_construct_while_loop_flow_chart.jpg		10_Looping_construct_while_loop_flow_chart.jpg
11_SV_Function_Concept_with_example.sv		11_SV_Function_Concept_with_example.sv
11_SV_Function_more_examples_for_practice.sv		11_SV_Function_more_examples_for_practice.sv
12_SV_Task_Concept_with_example.sv		12_SV_Task_Concept_with_example.sv
12_SV_Task_more_examples_for_practice.sv		12_SV_Task_more_examples_for_practice.sv
13_function_vs_task_similarity_and_difference.sv		13_function_vs_task_similarity_and_difference.sv
14_SV_process_disable_fork_with_example.sv		14_SV_process_disable_fork_with_example.sv
14_SV_process_fork_join_any_diagram.jpg		14_SV_process_fork_join_any_diagram.jpg
14_SV_process_fork_join_any_with_example.sv		14_SV_process_fork_join_any_with_example.sv
14_SV_process_fork_join_diagram.jpg		14_SV_process_fork_join_diagram.jpg
14_SV_process_fork_join_none_diagram.jpg		14_SV_process_fork_join_none_diagram.jpg
14_SV_process_fork_join_none_with_example.sv		14_SV_process_fork_join_none_with_example.sv
14_SV_process_fork_join_with_example.sv		14_SV_process_fork_join_with_example.sv
14_SV_process_mixed_examples_with_forkjoin_forkjoinany_forkjoinnone_waitedfork_disablefork.sv		14_SV_process_mixed_examples_with_forkjoin_forkjoinany_forkjoinnone_waitedfork_disablefork.sv
14_SV_process_waited_fork_with_example.sv		14_SV_process_waited_fork_with_example.sv
14_SV_processes_overview.sv		14_SV_processes_overview.sv
15_10_SV_deep_copy.sv		15_10_SV_deep_copy.sv
15_11_Shallow_copy_Vs_Deep_Copy_diagram.png		15_11_Shallow_copy_Vs_Deep_Copy_diagram.png
15_1_SV_Class_Concept_introduction.sv		15_1_SV_Class_Concept_introduction.sv
15_2_SV_Class_Accessing_unallocated_memory.sv		15_2_SV_Class_Accessing_unallocated_memory.sv
15_3_SV_Class_assignment_multple_handle_for_same_object_diagram.png		15_3_SV_Class_assignment_multple_handle_for_same_object_diagram.png
15_3_SV_Class_assignments.sv		15_3_SV_Class_assignments.sv
15_4_SV_Class_various_array_of_objects.sv		15_4_SV_Class_various_array_of_objects.sv
15_5_SV_Static_properties_or_variables_in_class.sv		15_5_SV_Static_properties_or_variables_in_class.sv
15_6_SV_Static_methods_in_class.sv		15_6_SV_Static_methods_in_class.sv
15_7_this_keyword_in_class_usage_and_example.sv		15_7_this_keyword_in_class_usage_and_example.sv
15_8_SV_Copying_technique.sv		15_8_SV_Copying_technique.sv
15_9_SV_Shallow_copy.sv		15_9_SV_Shallow_copy.sv
16_SV_Inheritance_concept_understanding_with_example.sv		16_SV_Inheritance_concept_understanding_with_example.sv
16_SV_Inheritance_tricky_imp_examples.sv		16_SV_Inheritance_tricky_imp_examples.sv
17_Super_keyword_in_class_usage_with_examples.sv		17_Super_keyword_in_class_usage_with_examples.sv
18_virtual_keyword_in_class_usage_with_examples.sv		18_virtual_keyword_in_class_usage_with_examples.sv
19_Virtual_or_Abstract_class_in_sv_usage_with_examples.sv		19_Virtual_or_Abstract_class_in_sv_usage_with_examples.sv
1_SV_Data_Types.sv		1_SV_Data_Types.sv
20_Polymorphism_concept_understanding_with_example.sv		20_Polymorphism_concept_understanding_with_example.sv
21_scope_resolution_operator_in_sv_usage_with_example.sv		21_scope_resolution_operator_in_sv_usage_with_example.sv
22_parameterized_classes_in_sv_with_example.sv		22_parameterized_classes_in_sv_with_example.sv
23_extern_method_concept_in_sv_with_example.sv		23_extern_method_concept_in_sv_with_example.sv
25_Data_Encapsulation_or_Data_Hiding_concept_understanding_with_example.sv		25_Data_Encapsulation_or_Data_Hiding_concept_understanding_with_example.sv
26_constant_class_properties_in_sv_with_example.sv		26_constant_class_properties_in_sv_with_example.sv
27_typedef_class_in_sv_with_example.sv		27_typedef_class_in_sv_with_example.sv
28_Randomization_technique_various_constraint_randomization_undrstanding_with_examples.sv		28_Randomization_technique_various_constraint_randomization_undrstanding_with_examples.sv
2_SV_Arrays_Overview.sv		2_SV_Arrays_Overview.sv
2_SV_Packed_Array_example1.sv		2_SV_Packed_Array_example1.sv
2_SV_Packed_Unpacked_Array_Mix_example1.sv		2_SV_Packed_Unpacked_Array_Mix_example1.sv
2_SV_Packed_vs_Unpacked_Array.sv		2_SV_Packed_vs_Unpacked_Array.sv
2_SV_Unpacked_Array_example1.sv		2_SV_Unpacked_Array_example1.sv
3_SV_Dynamic_Array_Overview.sv		3_SV_Dynamic_Array_Overview.sv
3_SV_Dynamic_Array_various_example.sv		3_SV_Dynamic_Array_various_example.sv
4_SV_Associative_Array_overview.sv		4_SV_Associative_Array_overview.sv
4_SV_associative_array_various_example.sv		4_SV_associative_array_various_example.sv
5_Array_Manipulation_Methods_overview.sv		5_Array_Manipulation_Methods_overview.sv
5_Array_itertor_index_querying_methods_with_example.sv		5_Array_itertor_index_querying_methods_with_example.sv
5_Array_locator_methods_with_example.sv		5_Array_locator_methods_with_example.sv
5_Array_ordering_methods_with_example.sv		5_Array_ordering_methods_with_example.sv
5_Array_reduction_methods_with_example.sv		5_Array_reduction_methods_with_example.sv
6_SV_Queue_concept_and_its_methods_Overview.sv		6_SV_Queue_concept_and_its_methods_Overview.sv
6_SV_Queue_various_examples.sv		6_SV_Queue_various_examples.sv
6_SV_bounded_vs_unbounded_Queue.jpg		6_SV_bounded_vs_unbounded_Queue.jpg
7_SV_structure_overview_with_example.sv		7_SV_structure_overview_with_example.sv
8_SV_Union_overview_with_example.sv		8_SV_Union_overview_with_example.sv
9_Various_if_statement_in_SV_with_example.sv		9_Various_if_statement_in_SV_with_example.sv
IEEE_standard_System_Verilog_LRM.pdf		IEEE_standard_System_Verilog_LRM.pdf
README.md		README.md
SV_Key_Points.sv		SV_Key_Points.sv
axi_trace.txt		axi_trace.txt
incdir_concept_cadence_xcelium_tool.sv		incdir_concept_cadence_xcelium_tool.sv
string_datatype.sv		string_datatype.sv
system_verilog_randomization_control.sv		system_verilog_randomization_control.sv
tb_clock_gen.sv		tb_clock_gen.sv
tb_using_typedef.sv		tb_using_typedef.sv

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