Detailed documentation Error Injection Tool
High energy particles will cause errors in electronic devices. This is a main problem in SRAM based FPGA since the configuration RAM is easily affected. The reliability of a hardware design in SRAM based FPGAs can be increased by using design mythologies like Triple Module Redundancy, EDAC Codes and or Scrubbing.
But a big problem is to test the implementation of these methods. The here documented tool aims to solve this problem.
The compare hardware is built around the radiation hardened design. The goal of the compare design is to run a test for the radiation hardened design.
The main part of the compare hardware is the golden design. This design has the same functionality like the radiation hardened design but it is not manipulated by induced errors. The radiation hardened design is the only component which is affected by induced errors.
The sequencer is a core which generates a test input for the design under test (DUT) and the golden design. For each clock cycle the compare core compares the outputs of the golden design and the DUT if it is the same a “C” for correct is written in the FIFO core. If the outputs differ an “E” for error is written into the FIFO.
The FIFO decouples the fast compare core from the slow running UART core. Until the sequence is running the FIFO is filled.
The UART core communicates with the computer. The UART core reads from the FIFO and writes the compare values to the computer.
Figure 2: GUI Error Injection Tool
To automate the bifile manipulation a tool is programmed in python. The GUI is developed in Qt with the PyQt4 binding to python.
In the GUI the user can easily set the conditions for a test run. First the two compare and design bitfile is added. This information is needed to generate the mask file for targeted manipulation of the DUT. Also the FPGA type is added and the number of error injects. Is the log box is set a copy of bitfiles causing an erroneous output is generated. At least the serial port is given to the application. Now the test can be started with the “Start injection” Button.
Figure 3: Abstract overview Error Injection Tool
The python code is separated in two classes and the main source, as seen in figure 3. In the constructor the GUI class loads the ui file. The ui file generated via Qt Designer. This allows to easily modifying the appearance of the GUI without changing the code. The functionality for the GUI, Button clicks, get functions from the entry forms and set functions for the text widget are programmed in the GUI class. This clearly separates GUI functionality from the rest of the code.
In bitfile class gives the functionallity for manipulation of bitfiles, parsing devices and generating mask files. To generate a mask file, two bitfiles (filename1, filename2) are necessary to calculate, which bytes are allowed to modify. The types.list file contains some FPGA device dependent offsets to calculate the mask file.
When the user filled all settings and presses the “start injection” button the mask file gets generated and then an automated test is started. Each induced error starts with the manipulation of the original bitfile. For that under consideration of the mask file a bit is randomly chosen and flipped. Now the FPGA is programmed with the manipulated bifile. For that Xilinx Impact is started in the batch Mode. That means impact is configured by a batchfile. After the programming step the python tool waits for a response from the FPGA. The response is validated if it is correct the next error is induced. If there is an incorrect response the bitfile is logged with a timestamp (if the log chechbox is set). The error injection stops when the number of induced errors is reached.
The tool was tested and used for a Spartan 3e1600 board with windows 7 operating system. The tool showed up some important consideration for implementing radiation hardened designs.