Chapter Guide

Chapter Guide

Every chapter with the questions it opens with and its sections. Click a chapter to read it on GitHub.

Part I — Electronic Devices

Every circuit, processor and converter in this book is built from a handful of semiconductor devices, and every abstraction it relies on (the amplifier, the logic gate, the switch, the instruction) holds only while those devices stay inside their limits. Part I turns device physics into the working knowledge needed to use real parts: how a nonlinear device is modelled at the level of accuracy a design requires, how it is biased and linearised, how its parameters move with temperature and from part to part, and what its datasheet guarantees. It moves from ideas common to all devices, through the junction and the two transistor families, to the power, wide-bandgap and optoelectronic devices that carry the same principles to kilovolts, gigahertz and light.

Part opener: part-1-electronic-devices/README.md

1. Electronic Device Fundamentals

How is a nonlinear device described, and how do engineers choose a model simple enough to design with but accurate enough to trust?

What is an operating point, why must it be set and stabilised, and when may the device be treated as linear around it?

Which parameters on a datasheet are guaranteed, which drift with temperature, and which practical limits end the validity of every model?

9 sections · 6 figures

• 1.1 Voltage–current characteristics
• 1.2 Nonlinear devices
• 1.3 Device models
• 1.4 Operating regions
• 1.5 Biasing
• 1.6 Small-signal concepts
• 1.7 Temperature effects
• 1.8 Device parameters
• 1.9 Practical limitations

2. Semiconductor Junction Devices

How does a real p–n junction depart from the ideal Shockley law in forward bias, reverse bias, breakdown and switching?

How are junctions specialised to rectify, regulate, switch fast, detect and emit light, convert sunlight, tune circuits and absorb transients, and what limits each?

Which datasheet parameters decide the choice of each device, and how are its losses and temperatures estimated?

10 sections · 6 figures

• 2.1 PN-junction operation
• 2.2 Diode characteristics
• 2.3 Rectifier diodes
• 2.4 Zener diodes
• 2.5 Schottky diodes
• 2.6 Photodiodes
• 2.7 LEDs
• 2.8 Solar cells
• 2.9 Varactor diodes
• 2.10 Protection diodes

3. Bipolar Junction Transistors

How do the BJT's structure and Ebers–Moll model explain its operating regions, current gain and saturation voltage?

How are the common-emitter, common-base and common-collector configurations different, and how is a transistor biased so that its operating point survives $\beta$ spread and temperature?

What limits a BJT's gain, switching speed and frequency response, and how are those limits calculated from datasheet parameters?

11 sections · 6 figures

• 3.1 BJT structure
• 3.2 Operating regions
• 3.3 Common-base configuration
• 3.4 Common-emitter configuration
• 3.5 Common-collector configuration
• 3.6 DC biasing
• 3.7 Load lines
• 3.8 Small-signal models
• 3.9 Amplification
• 3.10 Switching behavior
• 3.11 Frequency response

4. Field-Effect Transistors

How does a gate voltage control a channel, and which model of the drain current holds where?

How do threshold spread, body effect and temperature decide whether a biasing scheme or a switch design survives production?

What separates a power MOSFET from a signal MOSFET, and which datasheet limits govern it?

10 sections · 6 figures

• 4.1 JFET operation
• 4.2 MOSFET structure
• 4.3 Enhancement and depletion modes
• 4.4 Threshold voltage
• 4.5 Operating regions
• 4.6 DC biasing
• 4.7 Small-signal models
• 4.8 MOSFET amplification
• 4.9 MOSFET switching
• 4.10 Power MOSFET fundamentals

5. Advanced Semiconductor Devices

How do four-layer devices latch, and what makes them turn off or fail to?

What does an IGBT, a SiC MOSFET or a GaN HEMT offer that a silicon MOSFET does not, and at what price?

How are optoelectronic and compound-semiconductor devices specified, and how is any power device selected against its ratings?

9 sections · 6 figures

• 5.1 Thyristors
• 5.2 SCRs
• 5.3 TRIACs
• 5.4 DIACs
• 5.5 IGBTs
• 5.6 Wide-bandgap power devices
• 5.7 Optoelectronic devices
• 5.8 Compound-semiconductor devices
• 5.9 Device selection and ratings

Part II — Analog Electronics

Part I described devices one at a time. This part connects them into circuits that do continuous-valued work: rectifying the mains into a DC rail, amplifying a microvolt sensor signal, filtering it, making it oscillate on purpose or keeping it from oscillating by accident, and holding a reference voltage steady. A nonlinear device, biased and wrapped in feedback, behaves like a linear building block (a gain of 100, a 1 kHz low-pass filter, a 2.500 V reference), but only within the limits of swing, bandwidth, slew rate, noise, offset, temperature and stability that the device sets. A strain-gauge amplifier that drifts with the seasons, a regulator that oscillates when a ceramic capacitor is fitted, a rectifier whose capacitor dies after two summers: each is an abstraction pushed past its limits, and each is predicted by the methods of this part.

Part opener: part-2-analog-electronics/README.md

6. Diode Circuits

How much DC, ripple and stress does each rectifier circuit produce, and how are those numbers computed when a capacitor makes the diode current a pulse?

How do diodes reshape, limit, shift and multiply signals and protect inputs, and where do their non-ideal characteristics show?

What procedure turns a load specification into a transformer, diodes, capacitor and fuse that survive mains tolerance, inrush and a ten-year life?

10 sections · 6 figures

• 6.1 Half-wave rectifiers
• 6.2 Full-wave rectifiers
• 6.3 Bridge rectifiers
• 6.4 Rectifier performance
• 6.5 Ripple
• 6.6 Capacitor filtering
• 6.7 Clipping circuits
• 6.8 Clamping circuits
• 6.9 Voltage multipliers
• 6.10 Practical rectifier design

7. Transistor Amplifiers

How are the gain, input impedance and output impedance of a transistor stage computed, and how do they change when the stage is connected to a real source and load?

What sets an amplifier's bandwidth and its distortion, and what does an engineer do to improve each?

9 sections · 5 figures

• 7.1 Single-stage amplifiers
• 7.2 Small-signal analysis
• 7.3 Common-emitter amplifiers
• 7.4 Common-source amplifiers
• 7.5 Emitter and source followers
• 7.6 Multistage amplifiers
• 7.7 Input and output impedance
• 7.8 Frequency response
• 7.9 Distortion

8. Operational Amplifiers

How far can a circuit designer trust the two "golden rules" of the ideal op-amp, and which datasheet parameter breaks them first in a given application?

How are the standard op-amp circuits (amplifiers, integrators, comparators, instrumentation amplifiers, rectifiers, filters and oscillators) designed to a numerical specification?

10 sections · 6 figures

• 8.1 Ideal and practical op-amps
• 8.2 Inverting and non-inverting amplifiers
• 8.3 Summing and difference amplifiers
• 8.4 Integrators and differentiators
• 8.5 Comparators
• 8.6 Instrumentation amplifiers
• 8.7 Precision rectifiers
• 8.8 Active filters
• 8.9 Oscillators
• 8.10 Limitations and stability

9. Feedback and Oscillators

How does negative feedback change an amplifier's gain, bandwidth and impedances, and what decides whether a feedback amplifier is stable with a real load?

What conditions make a circuit oscillate at a well-defined frequency and amplitude, and how are RC, LC and crystal oscillators and waveform generators designed?

9 sections · 6 figures

• 9.1 Positive and negative feedback
• 9.2 Feedback topologies
• 9.3 Gain and bandwidth
• 9.4 Stability
• 9.5 Barkhausen criterion
• 9.6 RC oscillators
• 9.7 LC oscillators
• 9.8 Crystal oscillators
• 9.9 Waveform generators

10. Analog Integrated Circuits

How are the amplifiers, references and regulators that analog design takes for granted built from matched transistors on one die, and what in that construction sets their offset, gain, bandwidth, drift and stability?

How do comparators, DACs and ADCs turn those same building blocks into the interface between the analog world and the digital logic of Part III?

10 sections · 6 figures

• 10.1 Differential amplifiers
• 10.2 Current mirrors
• 10.3 Active loads
• 10.4 Multistage integrated amplifiers
• 10.5 Frequency compensation
• 10.6 Analog IC architecture
• 10.7 Voltage references
• 10.8 Regulators
• 10.9 Comparators
• 10.10 Mixed-signal interfaces

Part III — Digital Electronics

Part II ended where analog circuits hand their results to logic: a comparator decides, an ADC delivers a code. This part builds the digital half of electronics from that boundary. A bit is an abstraction imposed on a voltage, valid only while the voltage stays outside the undefined band and the clock leaves time for every signal to settle. Inside those limits digital design offers exact repeatability, cascading without accumulated noise, and designs that can be specified completely and verified on every input. Outside them come the characteristic digital failures: a field read with the wrong sign or byte order, an overflow that turns full forward into full reverse, a glitch that clocks a register, a synchroniser that fails once a month. This part develops the representations, logic, building blocks and timing rules that make synchronous digital systems work at first power-up and keep working.

Part opener: part-3-digital-electronics/README.md

11. Digital Number Systems

How are integers, signed values, fractions and real numbers represented in a fixed number of bits, and what does each representation cost in range, resolution and hardware?

What happens at the edges — overflow, wrap-around, rounding and conversion between formats — and how does an engineer detect and contain it?

8 sections · 5 figures

• 11.1 Binary, octal, decimal and hexadecimal
• 11.2 Signed number representation
• 11.3 Two's complement
• 11.4 Binary arithmetic
• 11.5 Overflow
• 11.6 Fixed-point arithmetic
• 11.7 Floating-point representation
• 11.8 Boolean variables

12. Boolean Algebra and Logic Gates

How are requirements turned into Boolean equations and truth tables, and how are those equations simplified into the smallest or fastest gate network?

What does a real logic gate guarantee — which functions, which voltage levels and noise margins, which delays — and where does the two-valued abstraction stop?

8 sections · 5 figures

• 12.1 Boolean algebra
• 12.2 Logic gates
• 12.3 Truth tables
• 12.4 De Morgan's laws
• 12.5 Boolean simplification
• 12.6 Karnaugh maps
• 12.7 Combinational logic
• 12.8 Logic minimization

13. Combinational Digital Systems

How are the standard combinational building blocks (adders, multiplexers, decoders, encoders, comparators, ALUs, code converters) organised, and how do their structures trade logic for speed?

How long does a combinational block take to produce a valid output, what changes that time, and how is it read from a datasheet or an FPGA timing report?

9 sections · 5 figures

• 13.1 Adders and subtractors
• 13.2 Multiplexers
• 13.3 Demultiplexers
• 13.4 Encoders
• 13.5 Decoders
• 13.6 Comparators
• 13.7 Arithmetic logic units
• 13.8 Code converters
• 13.9 Timing and propagation delay

14. Sequential Digital Systems

How are latches, flip-flops, registers, counters and shift registers built from gates and feedback, and how are they combined into finite-state machines?

What timing rules must a synchronous circuit obey, how fast can it be clocked, and what happens when a signal crosses between unrelated clocks or a reset is released at the wrong moment?

10 sections · 6 figures

• 14.1 Latches
• 14.2 Flip-flops
• 14.3 Registers
• 14.4 Counters
• 14.5 Shift registers
• 14.6 Finite-state machines
• 14.7 State encoding
• 14.8 Timing constraints
• 14.9 Clock-domain considerations
• 14.10 Reset strategies

15. Digital System Design

How is a digital system taken from a written specification to verified hardware, and which rules make the result robust?

How do glitches, asynchronous inputs and timing budgets break designs whose logic is correct, and how are they designed out and tested for?

9 sections · 5 figures

• 15.1 Design methodology
• 15.2 State diagrams
• 15.3 State tables
• 15.4 Hardware timing
• 15.5 Glitches
• 15.6 Synchronization
• 15.7 Memory elements
• 15.8 Logic implementation
• 15.9 Verification and test benches

Part IV — Computer Architecture and Digital Hardware

Part III built digital circuits from gates and flip-flops: adders, multiplexers, counters, state machines, all clocked and timed. This part assembles them into the machines that run almost every modern product — processors, memories and programmable logic — and into the languages used to design them. An instruction set lets software be written once and run on circuits that change every few years, but the abstraction leaks. A motor-control loop misses deadlines because of cache misses, a data logger dies because its flash wears out, an interrupt arrives late because of a priority set one line wrong, and an FPGA design fails timing because its routing is congested. This part explains the hardware beneath the instruction set and the netlist well enough to predict those failures with numbers.

Part opener: part-4-computer-architecture-and-digital-hardware/README.md

16. Computer Architecture

What does an instruction set promise to software, and how does a datapath and control unit keep that promise in hardware?

Why does a processor's speed depend so much on its pipeline and memory hierarchy, and how can it be estimated with numbers before code is run?

How do buses, interrupts and DMA connect a processor to memory and to the outside world?

11 sections · 6 figures

• 16.1 Computer organisation
• 16.2 Instruction sets
• 16.3 Registers
• 16.4 ALUs
• 16.5 CPU datapaths
• 16.6 Control units
• 16.7 Memory hierarchy
• 16.8 Caches
• 16.9 Buses
• 16.10 Interrupts
• 16.11 Input/output architecture

17. Microprocessors and Microcontrollers

How does a microcontroller core execute instructions, address memory and peripherals, and respond to interrupts — and with what latency?

How are timers, GPIO and serial peripherals organised at register level, and how are they combined so that hardware, not software, sets the timing?

When is a microcontroller the right choice, and when does a design need a microprocessor running an operating system?

10 sections · 6 figures

• 17.1 Processor architecture
• 17.2 Instruction execution
• 17.3 Memory maps
• 17.4 Addressing modes
• 17.5 Interrupt handling
• 17.6 Timers and counters
• 17.7 GPIO
• 17.8 Serial interfaces
• 17.9 Peripheral integration
• 17.10 Microprocessor versus microcontroller

18. Memory and Programmable Logic

How do SRAM, DRAM and flash store a bit, and what do their cell structures imply for speed, density, refresh, endurance and retention?

How is a memory connected to a processor, and what limits the bandwidth and latency actually achieved?

How does an FPGA implement arbitrary logic with look-up tables and programmable interconnect, and when is it worth using one to accelerate a computation?

10 sections · 6 figures

• 18.1 SRAM and DRAM
• 18.2 ROM and Flash
• 18.3 Memory interfaces
• 18.4 FPGA architecture
• 18.5 LUTs
• 18.6 Configurable logic blocks
• 18.7 Programmable interconnects
• 18.8 CPLDs
• 18.9 Hardware acceleration
• 18.10 FPGA applications

19. Hardware Description Languages

How does a textual description become flip-flops, look-up tables and wires, and which language constructs describe which hardware?

How do simulation, synthesis, timing constraints, test benches and assertions together establish that the hardware does what the design intends?

11 sections · 6 figures

• 19.1 HDL fundamentals
• 19.2 SystemVerilog
• 19.3 VHDL overview
• 19.4 Combinational logic descriptions
• 19.5 Sequential logic descriptions
• 19.6 Simulation
• 19.7 Synthesis
• 19.8 Timing constraints
• 19.9 Test benches
• 19.10 FPGA implementation
• 19.11 Hardware verification

Part V — Programming and Computational Systems

Parts III and IV built the machine: logic gates, registers, datapaths, memories, processors and programmable logic, ending with hardware described in a language. Part V turns to the software that runs on that machine and the software engineers write around it. An electronics engineer today programs constantly: firmware in C or C++ for the microcontroller inside a product, Python for acquiring and analysing measurements and automating a test rig, and numerical code for simulating a circuit, a filter or a control loop before it is built. These programs have finite word lengths, memory and time, and their failures (an accumulator that stops counting, a pointer that outlives its buffer, a result that cannot be reproduced) are as real as a resistor that overheats. This part treats programming as an engineering discipline, with the same habit as the rest of the book: state the model, know where it holds, and measure the consequence.

Part opener: part-5-programming-and-computational-systems/README.md

20. Programming Fundamentals

How does an engineer turn a calculation or a control rule into a correct, efficient program, and what does the machine actually do with variables, functions and data?

How are programs organised, made robust against bad inputs and failures, debugged and tested so that they stay correct as they grow?

10 sections · 5 figures

• 20.1 Algorithms
• 20.2 Variables and data types
• 20.3 Control flow
• 20.4 Functions
• 20.5 Arrays and data structures
• 20.6 Memory
• 20.7 Modular programming
• 20.8 Error handling
• 20.9 Debugging
• 20.10 Testing

21. C/C++ for Engineering

How do pointers, structures, memory allocation and bit operations map onto the memory and registers of a real machine?

How do C++ classes and object-oriented design help build safe firmware, and what do compilation, linking and the embedded coding standards demand?

10 sections · 5 figures

• 21.1 C fundamentals
• 21.2 Pointers
• 21.3 Structures
• 21.4 Memory management
• 21.5 Bitwise operations
• 21.6 Peripheral-oriented programming
• 21.7 C++ classes
• 21.8 Object-oriented design
• 21.9 Compilation and linking
• 21.10 Embedded-oriented C/C++

22. Python for Engineering

How does an engineer use Python and its numerical stack to turn raw measurements into trustworthy numbers and plots?

How are instruments and microcontrollers driven from Python, and how are the resulting data stored so that the experiment can be repeated?

10 sections · 5 figures

• 22.1 Python fundamentals
• 22.2 Numerical arrays
• 22.3 Data processing
• 22.4 Plotting and visualization
• 22.5 Scientific libraries
• 22.6 Signal analysis
• 22.7 Data acquisition
• 22.8 Automation scripts
• 22.9 File formats
• 22.10 Reproducible computational experiments

23. Algorithms and Data Structures

How is the cost of an algorithm predicted before it is run, and how does the choice of data structure set that cost?

Which classic structures and algorithms (lists, queues, trees, hash tables, sorting, searching, graph traversal, shortest paths) solve which engineering problems, and where do they fail?

10 sections · 5 figures

• 23.1 Complexity analysis
• 23.2 Arrays and linked lists
• 23.3 Stacks and queues
• 23.4 Trees and graphs
• 23.5 Hash tables
• 23.6 Searching and sorting
• 23.7 Numerical algorithms
• 23.8 Graph algorithms
• 23.9 Algorithm selection
• 23.10 Engineering applications

24. Scientific Computing

How are large engineering computations organised so that they run fast on real hardware: matrix libraries, sparse solvers, parallel cores and GPUs, profiling?

How are their results made trustworthy: precision choices, recorded environments, automated tests and version-controlled collaboration?

10 sections · 5 figures

• 24.1 Numerical computing environments
• 24.2 Matrix computation
• 24.3 Scientific data formats
• 24.4 Simulation workflows
• 24.5 Parallel computing fundamentals
• 24.6 Performance profiling
• 24.7 Numerical precision
• 24.8 Reproducibility
• 24.9 Software testing
• 24.10 Version control and collaborative workflows

Part VI — Embedded and Real-Time Systems

Parts IV and V built a processor and taught it to run programs. This part puts that processor inside a product — a water meter, a motor drive, a flight controller, an EV battery pack, an infusion pump — where it must sense and act on the physical world through pins and buses, meet deadlines set by physics, live within kilobytes of memory and microamps of current, and keep working unattended for a decade or more. The abstraction this part builds is the task: a piece of firmware with a period, a deadline and a worst-case execution time, which can be scheduled, analysed and proved to meet its timing. Like every abstraction in the book, it holds only inside limits — electrical limits at the pins, bit-timing limits on the buses, energy budgets from the battery, and timing limits that interrupts, shared resources and priority inversion can break. The four chapters move from the architecture of an embedded system, through its interfaces and its timing, to the engineering practice that ties them into a product that can be built, tested and maintained.

Part opener: part-6-embedded-and-real-time-systems/README.md

25. Embedded-System Architecture

How is an embedded system decomposed into hardware, firmware and peripherals, and how are its microcontroller, memory and energy chosen against measurable budgets?

Which firmware structure fits which timing problem, and how does a device boot and update itself safely in the field?

9 sections · 6 figures

• 25.1 Embedded-system models
• 25.2 Hardware–software partitioning
• 25.3 Microcontroller selection
• 25.4 Memory constraints
• 25.5 Power constraints
• 25.6 Firmware architecture
• 25.7 Peripheral drivers
• 25.8 Boot processes
• 25.9 Firmware updates

26. Embedded Interfaces

What electrical and timing limits govern GPIO and the common serial buses, and how are they designed in from the standards' numbers?

How are converters and sensors connected without losing accuracy, and how is a failing link diagnosed with a scope and logic analyser?

10 sections · 6 figures

• 26.1 GPIO
• 26.2 UART
• 26.3 SPI
• 26.4 I²C
• 26.5 CAN
• 26.6 USB fundamentals
• 26.7 Ethernet fundamentals
• 26.8 ADC and DAC interfaces
• 26.9 Sensor interfaces
• 26.10 Communication troubleshooting

27. Real-Time Computing

How are interrupt latency and task response times bounded, and how do scheduling policies and analysis prove that every deadline will be met?

What goes wrong when tasks share data and resources — races, deadlock, priority inversion — and how do synchronisation, RTOS services and watchdogs contain it?

11 sections · 6 figures

• 27.1 Real-time constraints
• 27.2 Interrupts
• 27.3 Scheduling
• 27.4 Timers
• 27.5 Concurrency
• 27.6 Race conditions
• 27.7 Synchronisation
• 27.8 Real-time operating systems
• 27.9 Task priorities
• 27.10 Latency and jitter
• 27.11 Watchdogs and fault handling

28. Embedded System Design

How is firmware structured so that drivers, protocols and application logic can be developed, replaced and tested independently, without hiding the timing and power behaviour that matter on real hardware?

How does an engineer budget energy, store data safely, find faults on a running target and prove that the firmware meets its requirements before it ships?

10 sections · 6 figures

• 28.1 Hardware abstraction
• 28.2 Firmware modularity
• 28.3 Device drivers
• 28.4 State machines
• 28.5 Low-power design
• 28.6 Data logging
• 28.7 Communications
• 28.8 Debugging
• 28.9 Hardware-in-the-loop testing
• 28.10 Firmware validation

Part VII — Power Electronics

Every electronic system draws its energy through a converter: a processor's 1.0 V rail, a phone charger, an electric car's 400 V inverter, a pump drive, a solar inverter. This part builds those converters. Its abstraction is the switching converter: semiconductor switches that are either fully on or fully off, alternating tens of thousands to millions of times a second, with inductors and capacitors that average the chopped waveform into the DC or AC voltage the load needs, at efficiencies of 95–99 %. Like every abstraction in the book, it holds only inside limits: the switching and conduction losses of real devices, the junction temperature those losses produce, the overshoot that stray inductance adds at every edge, the time a device survives a short circuit, and the frequency at which the averaged model stops describing what the circuit does. The four chapters move from the switch itself, through DC–DC and AC conversion, to the drives, chargers and grid converters in which power electronics meets machines and the power system.

Part opener: part-7-power-electronics/README.md

29. Power-Electronic Fundamentals

How much power does a semiconductor switch dissipate as it conducts and as it switches, and how do Si MOSFETs, IGBTs, SiC MOSFETs and GaN HEMTs compare with real datasheet numbers?

How are the junction temperature, the gate drive, the snubbers, the protection and the switching frequency chosen so that the switch is efficient and survives?

9 sections · 6 figures

• 29.1 Power switching
• 29.2 Semiconductor switch characteristics
• 29.3 Switching losses
• 29.4 Conduction losses
• 29.5 Thermal constraints
• 29.6 Gate driving
• 29.7 Snubbers
• 29.8 Protection
• 29.9 Switching-frequency trade-offs

30. DC–DC Converters

How do the buck, boost and buck–boost converters set their conversion ratios, what do their currents and voltages look like, and how are their inductors and capacitors sized for ripple, transients and efficiency?

What changes at light load when the inductor current reaches zero, and what model of the converter does its feedback loop see?

9 sections · 6 figures

• 30.1 Buck converter
• 30.2 Boost converter
• 30.3 Buck–boost converter
• 30.4 Continuous and discontinuous conduction
• 30.5 Converter waveforms
• 30.6 Inductor and capacitor sizing
• 30.7 Ripple
• 30.8 Efficiency
• 30.9 Feedback control interface

31. AC–DC and DC–AC Conversion

How do diode and thyristor rectifiers turn AC into DC, and what do overlap, firing angle and pulse number cost the supply?

How does a PWM inverter synthesise AC from a DC link, what spectrum does it produce, and how are its filter, switches, protection and heatsink chosen?

9 sections · 5 figures

• 31.1 Controlled and uncontrolled rectifiers
• 31.2 Inverters
• 31.3 PWM
• 31.4 Single-phase and three-phase inverters
• 31.5 Harmonics
• 31.6 Filtering
• 31.7 Switching strategies
• 31.8 Semiconductor selection
• 31.9 Protection and thermal design

32. Motor Drives and Power Conversion

How are rectifiers, inverters and DC–DC stages combined into motor drives, battery chargers and renewable-energy converters, and what does each interface (cable, motor, battery, PV array, grid) demand of the hardware?

How are regeneration, synchronisation and current control implemented at the circuit level, and where do they break?

9 sections · 6 figures

• 32.1 Power-electronic drive architectures
• 32.2 DC motor drives
• 32.3 Induction motor drive interfaces
• 32.4 Variable-frequency drives
• 32.5 Converter-fed machines
• 32.6 Regenerative operation
• 32.7 Battery charging
• 32.8 Renewable-energy converters
• 32.9 Grid-connected converter fundamentals

Part VIII — Integrated Circuits and VLSI

Every circuit in this book so far has ended up, sooner or later, inside a chip: the op-amp of Part II, the gates and flip-flops of Part III, the processor and memories of Part IV, the microcontroller that runs the firmware of Part VI and the gate driver and controller of a power converter in Part VII. This part opens the chip. It starts from the complementary MOS inverter, the circuit of which billions of copies make up a modern processor, and shows how its switching threshold, noise margins, power and delay follow from the transistor models of Chapter 4. It then scales up to the design flow that turns a register-transfer description of millions of gates into a placed, routed, timed and verified layout ready for fabrication, and ends at the system level, where an engineer decides which parts of a computation belong in software on a processor and which in dedicated hardware. The thread is the same as in the rest of the book: an abstraction (a logic gate, a standard cell, a synthesised netlist, an accelerator) holds only inside limits of voltage, delay, power and area that the devices beneath it set, and good design is knowing where those limits are.

Part opener: part-8-integrated-circuits-and-vlsi/README.md

33. CMOS Fundamentals

Why does a pair of complementary MOSFETs make an almost ideal logic gate, and what sets its noise margins, power and delay?

How are gates, latches and flip-flops built and sized at the transistor level, and how does a transistor schematic become a layout?

8 sections · 5 figures

• 33.1 CMOS logic
• 33.2 MOSFET switching
• 33.3 Static and dynamic power
• 33.4 Propagation delay
• 33.5 Noise margins
• 33.6 CMOS gates
• 33.7 Latches and flip-flops
• 33.8 Layout fundamentals

34. VLSI Design

How does a design described as registers and logic become a manufacturable layout, and which models decide whether it meets timing, power and area?

Where does each abstraction of the VLSI flow — the synthesised netlist, the timing graph, the power estimate, the design rules — hold, and where does the silicon depart from it?

10 sections · 5 figures

• 34.1 Design hierarchy
• 34.2 RTL design
• 34.3 Logic synthesis
• 34.4 Physical design
• 34.5 Placement and routing
• 34.6 Timing analysis
• 34.7 Power estimation
• 34.8 Design-rule checking
• 34.9 Verification
• 34.10 Fabrication constraints

35. Hardware–Software Co-Design

Which parts of a computation belong in software on a processor, and which in an FPGA, a GPU, an NPU or an ASIC — and what will the split really gain?

How do memory traffic, numerical precision and deadlines limit an accelerated system, and how is the combination verified before it is built?

8 sections · 6 figures

• 35.1 Partitioning computation
• 35.2 Processor versus FPGA
• 35.3 Hardware acceleration
• 35.4 Memory and data movement
• 35.5 Performance modeling
• 35.6 Embedded AI deployment
• 35.7 Real-time constraints
• 35.8 System-level verification