[BUG] vhdl_ls does not recognize two types are the same, when the modelsim and ghdl compiler does.

[CheezuzCrust]

Hey everyone, I got a tricky one for you today...

(VHDL-2008)

Let's start with the minimal recreation example:

file 1: generic_record_pkg.vhd ( a simple generic package which contains only one generic package)

library ieee;
use ieee.std_logic_1164.all;

package generic_record_pkg is
   generic(
      g_length : natural
   );

   type generic_record is record
      field: std_logic_vector(g_length-1 downto 0);
   end record;
end package;

file 2: generic_pt_using_generic_record_pkg.vhd

library ieee;
use ieee.std_logic_1164.all;

use work.generic_record_pkg;

package generic_pt_using_generic_record_pkg is
   generic(
      package i_generic_record_pkg is new generic_record_pkg generic map(<>)
   );

   type pt_returns_generic_record is protected
      function return_generic_record return i_generic_record_pkg.generic_record;
   end protected;
end package;

package body generic_pt_using_generic_record_pkg is
   type pt_returns_generic_record is protected body
      function return_generic_record return i_generic_record_pkg.generic_record is
         variable v_generic_record : i_generic_record_pkg.generic_record;
      begin
         v_generic_record.field := (others => '0');
         return v_generic_record;
      end function;
   end protected body;
end package body;

file 3: testbench with vhdl_ls problem

library ieee;
use ieee.std_logic_1164.all;

entity tb_playground is
end entity;

use work.generic_record_pkg;
use work.generic_pt_using_generic_record_pkg;

architecture arch of tb_playground is
   package i_gen_rec_pkg is new generic_record_pkg generic map(2);
   package i_gen_pt_using_gen_record is new generic_pt_using_generic_record_pkg generic map(i_gen_rec_pkg);
   shared variable sv_returns_generic_record : i_gen_pt_using_gen_record.pt_returns_generic_record;
   constant c_watchdog_period : time := 100 us;
begin
   p_gen_stuff: process
      variable v_gen_rec : i_gen_rec_pkg.generic_record;
   begin
      v_gen_rec := sv_returns_generic_record.return_generic_record; --VHDL_LS DOES NOT LIKE THIS LINE: "Invalid call to 'return_generic_method'
      report "the result is" & to_string(v_gen_rec.field);
      wait;
   end process;
end architecture;

The modelsim and GHDL simulators accept this code and compile just fine. VHDL_LS seems to not understand that the output type of return_generic_record is the same type as v_gen_rec.

Any help is appreciated! Also if you know a better way to do this kind of things :)