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2 changes: 1 addition & 1 deletion test/core/simd/meta/simd_f32x4.py
Original file line number Diff line number Diff line change
Expand Up @@ -350,7 +350,7 @@ def get_unknown_operator_case(self, cases):
unknown_op_cases = ['\n\n;; Unknown operators\n']
cases.extend(unknown_op_cases)

for lane_type in ['i8x16', 'i16x8', 'i32x4']:
for lane_type in ['i8x16', 'i16x8', 'i32x4', 'i64x2']:

for op in self.UNARY_OPS:
cases.append(tpl_assert.format(lane_type=lane_type, op=op, value=self.v128_const('i32x4', '0')))
Expand Down
43 changes: 25 additions & 18 deletions test/core/simd/meta/simd_int_arith2.py
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
"""

from simd import SIMD
from test_assert import AssertReturn, AssertInvalid
from test_assert import AssertReturn, AssertInvalid, AssertMalformed
from simd_lane_value import LaneValue
from simd_integer_op import IntegerSimpleOp as IntOp

Expand All @@ -17,7 +17,7 @@ class SimdLaneWiseInteger:

BINARY_OPS = ('min_s', 'min_u', 'max_s', 'max_u',)

class_summary = """;; Tests for {lane_type} [min_s, min_u, max_s, max_u] operations."""
class_summary = """;; Tests for {lane_type} [min_s, min_u, max_s, max_u, avgr_u] operations."""

def __init__(self):

Expand Down Expand Up @@ -246,21 +246,15 @@ def gen(case_data):
@property
def gen_test_case_unknown_operators(self):
"""generate unknown operators test cases"""

if self.LANE_TYPE != 'i32x4':
return ''

cases = '\n\n;; Unknown operators'
lane_types = ('f32x4', 'i64x2',)
assert_template = '(assert_malformed (module quote "(memory 1) (func (result v128) ({lane_type}.{op} {param_1} {param_2}))") "unknown operator")'
for lane_type in lane_types:
for op in self.BINARY_OPS:
cases += '\n' + assert_template.format(lane_type=lane_type,
op=op,
param_1=SIMD.v128_const('0', self.LANE_TYPE),
param_2=SIMD.v128_const('1', self.LANE_TYPE))

return cases
cases = ['\n\n;; Unknown operators']

for op in self.UNKNOWN_OPS:
cases.append(AssertMalformed.get_unknown_op_test(
op, 'v128',
SIMD.v128_const('0', self.LANE_TYPE),
SIMD.v128_const('1', self.LANE_TYPE)
))
return '\n'.join(cases)

@property
def gen_test_case_type_check(self):
Expand Down Expand Up @@ -373,15 +367,28 @@ def gen_test_cases(self):

class Simdi32x4Case(SimdLaneWiseInteger):
LANE_TYPE = 'i32x4'
class_summary = """;; Tests for {lane_type} [min_s, min_u, max_s, max_u] operations."""

UNKNOWN_OPS = ('f32x4.min_s', 'f32x4.min_u', 'f32x4.max_s', 'f32x4.max_u',
'i64x2.min_s', 'i64x2.min_u', 'i64x2.max_s', 'i64x2.max_u',
'f64x2.min_s', 'f64x2.min_u', 'f64x2.max_s', 'f64x2.max_u')


class Simdi16x8Case(SimdLaneWiseInteger):
LANE_TYPE = 'i16x8'

BINARY_OPS = ('min_s', 'min_u', 'max_s', 'max_u', 'avgr_u')
UNKNOWN_OPS = ('i16x8.avgr', 'i16x8.avgr_s')


class Simdi8x16Case(SimdLaneWiseInteger):
LANE_TYPE = 'i8x16'

BINARY_OPS = ('min_s', 'min_u', 'max_s', 'max_u', 'avgr_u')
UNKNOWN_OPS = ('i32x4.avgr_u', 'f32x4.avgr_u',
'i64x2.avgr_u', 'f64x2.avgr_u',
'i8x16.avgr', 'i8x16.avgr_s')


def gen_test_cases():
simd_i32x4_case = Simdi32x4Case()
Expand All @@ -395,4 +402,4 @@ def gen_test_cases():


if __name__ == '__main__':
gen_test_cases()
gen_test_cases()
10 changes: 10 additions & 0 deletions test/core/simd/meta/simd_integer_op.py
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@

from simd_lane_value import LaneValue


class IntegerSimpleOp:
"""Common integer simple ops:
min_s, min_u, max_s, max_u
Expand Down Expand Up @@ -47,6 +48,15 @@ def binary_op(op: str, p1: str, p2: str, lane_width: int) -> str:
else:
return p1 if i1 >= i2 else p2

elif op == 'avgr_u':
i1 = IntegerSimpleOp.get_valid_value(v1, lane_width, signed=False)
i2 = IntegerSimpleOp.get_valid_value(v2, lane_width, signed=False)
result = (i1 + i2 + 1) // 2
if base1 == 16 or base2 == 16:
return hex(result)
else:
return str(result)

else:
raise Exception('Unknown binary operation')

Expand Down
11 changes: 11 additions & 0 deletions test/core/simd/meta/test_assert.py
Original file line number Diff line number Diff line change
Expand Up @@ -78,3 +78,14 @@ def str_with_space(input_str):
}

return arg_empty_test.format(**param_map)


class AssertMalformed:
"""Generate an assert_malformed test"""

@staticmethod
def get_unknown_op_test(op, result_type, *params):
malformed_template = '(assert_malformed (module quote "(memory 1) (func (result {result_type}) ({operator} {param}))") "unknown operator")'
return malformed_template.format(
operator=op, result_type=result_type, param=' '.join(params)
)
3 changes: 3 additions & 0 deletions test/core/simd/simd_f32x4.wast
Original file line number Diff line number Diff line change
Expand Up @@ -2331,6 +2331,9 @@
(assert_malformed (module quote "(memory 1) (func (result v128) (i32x4.abs (v128.const i32x4 0 0 0 0)))") "unknown operator")
(assert_malformed (module quote "(memory 1) (func (result v128) (i32x4.min (v128.const i32x4 0 0 0 0) (v128.const i32x4 0 0 0 0)))") "unknown operator")
(assert_malformed (module quote "(memory 1) (func (result v128) (i32x4.max (v128.const i32x4 0 0 0 0) (v128.const i32x4 0 0 0 0)))") "unknown operator")
(assert_malformed (module quote "(memory 1) (func (result v128) (i64x2.abs (v128.const i32x4 0 0 0 0)))") "unknown operator")
(assert_malformed (module quote "(memory 1) (func (result v128) (i64x2.min (v128.const i32x4 0 0 0 0) (v128.const i32x4 0 0 0 0)))") "unknown operator")
(assert_malformed (module quote "(memory 1) (func (result v128) (i64x2.max (v128.const i32x4 0 0 0 0) (v128.const i32x4 0 0 0 0)))") "unknown operator")

;; type check
(assert_invalid (module (func (result v128) (f32x4.abs (i32.const 0)))) "type mismatch")
Expand Down
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