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@tlively tlively commented Mar 4, 2019

Separate each lane index because they are always interpreted
independently.

Separate each lane index because they are always interpreted
independently.
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tlively commented Mar 4, 2019

@binji does this seem reasonable to you? I don't think this is what WABT does currently.

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binji commented Mar 4, 2019

Seems reasonable to me, shouldn't be too hard to update wabt for this.

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gnzlbg commented Mar 4, 2019

I started working on a watb PR, I’ll try to submit it tomorrow

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LGTM!

@tlively tlively merged commit a289c58 into master Mar 5, 2019
@tlively tlively deleted the v8x16-shuffle-text branch March 5, 2019 02:09
gnzlbg added a commit to gnzlbg/wabt that referenced this pull request Mar 5, 2019
The textual (WAT) representation of the vector shuffle immediate argument was
underspecified. Recently, WebAssembly/simd#67 specified
it to be `i8x16.shuffle i5 i5 ... i5` (16 times `i5`), which is what all other
implementations were doing. WABT was reading the shuffle argument as 4 32-bit
hex integers that specified a `v128`, that is, `i8x16.shuffle 0x0 0x0 0x0 0x0`.

This PR updates WABT to conform to the modified draft of the SIMD extension.

Since there are more shuffle and permtue intrinsics in the WASM SIMD extension
pipeline, this PR adds a generic `iNxM` class implementing a packed array of `M`
`N`-bit wide integers.

The class can store the integer array in both textual and binary
representations. The textual repr is useful for WAT and type-checking, while the
binary repr is useful for the binary encoding.
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gnzlbg commented Mar 5, 2019

PR implementing this in WABT WebAssembly/wabt#1032

gnzlbg added a commit to gnzlbg/wabt that referenced this pull request Mar 5, 2019
The textual (WAT) representation of the vector shuffle immediate argument was
underspecified. Recently, WebAssembly/simd#67 specified
it to be `i8x16.shuffle i5 i5 ... i5` (16 times `i5`), which is what all other
implementations were doing. WABT was reading the shuffle argument as 4 32-bit
hex integers that specified a `v128`, that is, `i8x16.shuffle 0x0 0x0 0x0 0x0`.

This PR updates WABT to conform to the modified draft of the SIMD extension.

Since there are more shuffle and permtue intrinsics in the WASM SIMD extension
pipeline, this PR adds a generic `iNxM` class implementing a packed array of `M`
`N`-bit wide integers.

The class can store the integer array in both textual and binary
representations. The textual repr is useful for WAT and type-checking, while the
binary repr is useful for the binary encoding.
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binji commented Mar 5, 2019

So we're clear, the intention is to encode this as 16 immediate bytes, with each expected to be in the range [0,31], right? So it's a validation error if the values are out-of-range?

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gnzlbg commented Mar 5, 2019

So we're clear, the intention is to encode this as 16 immediate bytes, with each expected to be in the range [0,31], right?

I don't think that's the intent. The binary encoding (https://github.com/WebAssembly/simd/blob/master/proposals/simd/BinarySIMD.md#simd-instruction-encodings) says that the immediate mode argument is a LaneIdx32[16], that's 16 lane indices in range [0, 32), also 16 5-bit values. This matches the clarifications done in https://github.com/WebAssembly/simd/pull/30/files#diff-28263aca205221ef5f3c6b4a232654c3R293 / (e.g. see how it specifies that LaneIdx32[16] is 10 bytes wide (5 bit * 16 = 80 bits = 10 bytes):

This instruction is encoded with 10 bytes providing the indices of the elements to return. The indices i in range [0, 15] select the i-th element of a.

Otherwise the binary encoding would just use ImmBytes[16], to denote that the immediate mode operand contains 16 bytes.

So it's a validation error if the values are out-of-range?

This binary encoding does not need validation beyond the immediate mode argument being 10 bytes wide, because the 5-bit integers are always in range.

The textual encoding represents the shuffle arguments as natural numbers, which has to be validated (to avoid negative values, floating point, etc.), and these natural numbers have also to be validated to be in-range [0, 32).

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binji commented Mar 5, 2019

I see, it would be good to get everyone to sign off on that and land that PR first, since the current documentation is pretty explicit about it being one byte per lane index: https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#shuffle-lanes

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gnzlbg commented Mar 5, 2019

This parts of the docs is also very explicit about that: https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#immediate-operands

cc @lemaitre Using one byte per lane would make the WASM implementation significantly simpler, and would only introduce a small cost in binary size. What was the rationale for making the immediate mode operands as small as possible ?

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tlively commented Mar 5, 2019

This PR only uses i5 as part of the text format because that conveys the bounds information using conventions already set forth in the WebAssembly spec text. It is not meant to change the binary format from using one byte per index (16 index bytes total).

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gnzlbg commented Mar 5, 2019

@tlively yes, its the other PR open which does that change. For some reason (maybe because the actual instructions use bitpacked indices?) I thought that change was a bug fix as well, but I can't find any discussion about it anywhere.

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lemaitre commented Mar 6, 2019

cc @lemaitre Using one byte per lane would make the WASM implementation significantly simpler, and would only introduce a small cost in binary size. What was the rationale for making the immediate mode operands as small as possible ?

I just opened a discussion on my PR: #30

But to sum up, I just made an unverified assumption.
This has nothing to do with this PR anyway as it is about the textual representation only.

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5 participants