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Specify v8x16.shuffle text format #67
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Separate each lane index because they are always interpreted independently.
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@binji does this seem reasonable to you? I don't think this is what WABT does currently. |
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Seems reasonable to me, shouldn't be too hard to update wabt for this. |
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I started working on a watb PR, I’ll try to submit it tomorrow |
gnzlbg
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LGTM!
The textual (WAT) representation of the vector shuffle immediate argument was underspecified. Recently, WebAssembly/simd#67 specified it to be `i8x16.shuffle i5 i5 ... i5` (16 times `i5`), which is what all other implementations were doing. WABT was reading the shuffle argument as 4 32-bit hex integers that specified a `v128`, that is, `i8x16.shuffle 0x0 0x0 0x0 0x0`. This PR updates WABT to conform to the modified draft of the SIMD extension. Since there are more shuffle and permtue intrinsics in the WASM SIMD extension pipeline, this PR adds a generic `iNxM` class implementing a packed array of `M` `N`-bit wide integers. The class can store the integer array in both textual and binary representations. The textual repr is useful for WAT and type-checking, while the binary repr is useful for the binary encoding.
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PR implementing this in WABT WebAssembly/wabt#1032 |
The textual (WAT) representation of the vector shuffle immediate argument was underspecified. Recently, WebAssembly/simd#67 specified it to be `i8x16.shuffle i5 i5 ... i5` (16 times `i5`), which is what all other implementations were doing. WABT was reading the shuffle argument as 4 32-bit hex integers that specified a `v128`, that is, `i8x16.shuffle 0x0 0x0 0x0 0x0`. This PR updates WABT to conform to the modified draft of the SIMD extension. Since there are more shuffle and permtue intrinsics in the WASM SIMD extension pipeline, this PR adds a generic `iNxM` class implementing a packed array of `M` `N`-bit wide integers. The class can store the integer array in both textual and binary representations. The textual repr is useful for WAT and type-checking, while the binary repr is useful for the binary encoding.
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So we're clear, the intention is to encode this as 16 immediate bytes, with each expected to be in the range [0,31], right? So it's a validation error if the values are out-of-range? |
I don't think that's the intent. The binary encoding (https://github.com/WebAssembly/simd/blob/master/proposals/simd/BinarySIMD.md#simd-instruction-encodings) says that the immediate mode argument is a
Otherwise the binary encoding would just use
This binary encoding does not need validation beyond the immediate mode argument being 10 bytes wide, because the 5-bit integers are always in range. The textual encoding represents the shuffle arguments as natural numbers, which has to be validated (to avoid negative values, floating point, etc.), and these natural numbers have also to be validated to be in-range |
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I see, it would be good to get everyone to sign off on that and land that PR first, since the current documentation is pretty explicit about it being one byte per lane index: https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#shuffle-lanes |
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This parts of the docs is also very explicit about that: https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#immediate-operands cc @lemaitre Using one byte per lane would make the WASM implementation significantly simpler, and would only introduce a small cost in binary size. What was the rationale for making the immediate mode operands as small as possible ? |
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This PR only uses |
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@tlively yes, its the other PR open which does that change. For some reason (maybe because the actual instructions use bitpacked indices?) I thought that change was a bug fix as well, but I can't find any discussion about it anywhere. |
I just opened a discussion on my PR: #30 But to sum up, I just made an unverified assumption. |
Separate each lane index because they are always interpreted
independently.