PCB-Design-Skill v2.0.0

PCB-Design-Skill v2.0.0

这一版集中改进从产品想法到 PCB 交付的使用体验，并将此前开发版的检查能力一起发布。

• 从现有需求和检查记录生成简短的当前阶段与下一步，区分需要用户决定的产品问题和 Agent 应自行修复的记录问题。完整 G5 校验未通过时，不会显示制造证据已完成。
• 引入外部基础工程快照核对：锁定来源版本，检查可编辑原理图、PCB、许可依据和文件哈希。许可适用性、原生导入和电路正确性仍需分别审查。
• 更新中英文说明、产品目标及交付模板，让初次使用者能从一句想法开始，并在交接时知道当前拿到了什么、下一步由谁做。
• 收录开发版的离线批量检查、尺寸核对、PCBA 装配数据、工作状态、衍生板和制造文件版本核查。四套内置工具及七个运行依赖版本保持不变。

Windows 环境下完成 464 项 Python 测试、81 项 Node 测试，零失败、零跳过；Release ZIP 已在解压后验证文件清单和 SHA-256。测试范围是软件和模拟桥接客户端。本版没有新增整板 G0–G5 实测、原生 PCB 布线回滚、实板焊接和上电验证。详见仓库内 VALIDATION.md。

安装：下载 PCB-Design-Skill-v2.0.0.zip，完整解压后按 START_HERE.md 配置；不要只替换 SKILL.md。PCB-Design-Skill-v2.0.0.zip.sha256 用于核对下载文件。

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V2.0.0 improves the beginner path from a product idea to a PCB handoff. A read-only progress helper identifies the next action from project records; an external-source inventory checks pinned editable files and hashes without treating them as licensed or electrically proven. The release also includes offline, mechanical, PCBA, variant and derivative checks from the development branch. The four bundled toolsets and seven runtime dependencies remain at their pinned versions.

Validation: 464 Python and 81 Node tests passed with no skips, and the extracted release ZIP passed its manifest check. Complete board design, live PCB routing rollback, assembly and physical bring-up were not revalidated in this release.

v1.8.0 · Intake, calculations and guarded workflows

v1.8.0

• 新手两步确认：先梳理用途、载体、尺寸、供电、按钮接口和装配方式，再展示带尺寸与预算的方案。保留已确认内容和明确委派。
• 自动计算：增加 I²C 上拉、限定模型内的微带线阻抗与线宽反算；校验网页计算结果的输入、单位、模型和证据。
• 受控操作：区分新设计与已授权的局部维修，绑定具体输入并检查陈旧证据；保持原生读回、碰撞/越界拦截和回滚。
• 诊断与性能：引脚连接错误提供对象和修复线索，外形检查裁剪无关配对，统一回归入口拒绝把跳过测试当作完整验证。
• 文档：更新中英文 README、上手流程、计算适用范围及第三方来源。四套内置工具与七个运行依赖未变。

验证

409 项 Python 测试、81 项 Node 测试、独立桥接冒烟检查全部通过，无跳过项。另在真实 EasyEDA test1 上验证碰撞/越界拒绝、合法移动、保存重开和回滚后读回一致。48 组独立模型参考值用于微带线数值校验。

未把整板 G0–G5 新手实测、原生 PCB 布线回滚、网页计算器完整自动操作或实板电气性能列为已验证能力。详见 VALIDATION.md。

Install

Download the complete ZIP and keep its references, assets and vendor folders together. The SHA-256 sidecar verifies the downloaded archive. Existing projects retain their evidence; new-design gates need the sourced intake record. Review START_HERE.md and the migration notes before resuming a project.

v1.7.0 · 验收、几何检查与成本规划

v1.7.0

本版汇总 v1.6.0 之后的验收、PCB 几何检查、元件成本规划与文档更新。

主要更新

• 从想法梳理功能与 BOM，查询元件报价，区分用量成本与计入起订量、包装倍数后的采购金额；兼容替代料保留已确认的功能和性能。
• 增加 G0–G9 必检清单与需求覆盖核对。报告绑定实际源文件、基线和哈希，避免旧报告用于改动后的工程。
• 完善无连线原理图的受控移动、约束预检、回读、保存重开和恢复；增加摘要、分页、差异读取与输出预算。
• 修复板框断线、凹口与槽孔边距、同号多焊盘、非金属化孔跨层导通和过孔层跨度的误判。
• 保护走线按实际几何与基线比较。阻焊检查使用开窗并集和真实宏定义，空数据与未支持的几何不能获得 PASS。
• 重整中英文 README、安装升级指南、验证记录和第三方清单。随包包含 4 套工具／方法库和 7 个 JavaScript 运行依赖；外部接入项目单独列明。

验证与范围

356 项软件回归通过，另有 17 个工具自检通过，无跳过项。独立 CLI 审查发现的 4 个额外漏检已修复并复验关闭。test1 的无连线原理图移动、拦截、保存重开和恢复已有原生 EDA 实测记录。

整板 G0–G5、macOS 全流程、外部布线器互操作及本轮改进后的实板制造仍待验证。PCB 原生写入和布线回滚尚未实现；具体几何与宏解析边界见仓库 VALIDATION.md 和检查工具说明。

安装

下载 PCB-Design-Skill-v1.7.0.zip，完整解压并替换 Skill 安装入口，再新开对话。不要只覆盖 SKILL.md。包内包含第三方工具和所需桥接／格式校验依赖；Node.js、Python、嘉立创EDA客户端和 Run API Gateway 需另行准备。已有桥接进程请按 START_HERE.md 更新。附件 .sha256 用于核对 ZIP 文件。

English

v1.7.0 consolidates component-cost planning, requirement/check evidence bindings, guarded unwired-schematic operations, bounded data access and physical inspection corrections. Geometry fixes cover outline continuity, edge margins, repeated lands, plating, via spans, protected routing and actual mask-opening/macro semantics. Empty and unsupported input cannot establish acceptance.

The recorded software run passed 356 regression cases and 17 additional toolkit self-test commands. Native test1 evidence covers scoped unwired schematic movement and recovery; full-board, macOS, external-router and physical-manufacturing qualification remain pending. Native PCB writing/routing rollback is not implemented.

Install the complete ZIP, retain its vendor directories and start a fresh conversation. Both READMEs and THIRD_PARTY_NOTICES.md list the four bundled tools/methods packages, seven JavaScript runtime dependencies and external-only integrations. Full changes and evidence are in CHANGELOG.md and VALIDATION.md.

v1.6.0 · Guarded native EDA operations

v1.6.0 · 真实 EDA 受控写入 / Guarded live EDA writes

• 新增原生无连线原理图元件移动入口，支持写前碰撞、越界、源状态和字段检查。
• 正向写入与反向恢复保留完整可写属性；修复实测发现的仅传坐标导致扩展属性丢失问题。
• 新增逐步回读、保存重开验证、幂等操作 ID、日志锁和受控补偿；未知现场停止恢复。
• test1 实测通过合法移动、碰撞/越界拦截、保存重开及回滚后完整快照比对。
• 14 项新增自动化测试覆盖故障注入、自动补偿、并发改动阻断与重载差异；既有 52 项相邻测试复测。

Native movement now uses a typed Gateway entrypoint with preflight, full writable-property preservation, readback, save/reopen and guarded inverse operations. Native tests ran on test1; injected failure compensation was tested with mocks. Global interception of arbitrary calls, wired schematic edits and PCB routing rollback remain outside this release.

v1.5.2 · Batch preflight and repair feedback

v1.5.2 · 批次预检与修复反馈 / Batch preflight and repair feedback

中文

• 新增 G2-A 完整布局批次预检：读取新鲜源数据，计算所有目标对象和分区后的状态，检查几何及保护属性，再交给选定后端执行。
• 输出结构化修复报告：记录对象、预期值、实际值、失败检查及候选动作；身份、引脚、属性异常和重载失败不会直接生成移动指令。
• 新增持久化重试账本：阻止同计划与同适配器原样重试，识别重复失败，限制连续无进展，并支持幂等记录。
• 补充后端版本、原始观测和读回证据的对应要求；制造与供应信息保持可配置，不引入硬编码费用或库存门槛。
• 新增 11 项离线回归测试；复测相邻数据恢复和布局工具。更新中英文 README 与操作说明。

English

• Add full-target G2-A layout batch preflight using fresh source data, geometry and protected properties before handoff to the selected backend.
• Emit structured repair evidence with expected/actual values, objects, failed checks and scoped proposals. Identity, pin/property and reload failures do not authorize movement.
• Add a persistent, idempotent attempt ledger that blocks unchanged retries, detects repeated failures and bounds unsuccessful attempts.
• Document adapter revisions, raw captures and native readback evidence. Keep manufacturing/supply policies configurable; add no hard-coded fees or stock threshold.
• Add 11 offline regression tests and rerun adjacent data/recovery and layout tests. Update both READMEs and the execution guide.

范围 / Scope

本版本支持已测量的无连线分区布局。它不拦截任意官方 API、不自动执行修复、不求解电气意图、不回滚实时 EDA；真实 EDA 采集、写入和保存重载仍需后端联调。测试使用合成数据，未验证实板或 Token 节省比例。

This release covers measured unwired block layouts. It does not intercept arbitrary official API calls, execute repairs, solve electrical intent or roll back live EDA. Native capture, application and save/reload still require backend integration. Tests use synthetic data; no hardware or token-saving benchmark is claimed.

v1.5.1 · Data, layout and recovery

v1.5.1 · 数据核对、布局规划与操作恢复 / Data, layout and recovery

中文

• 增加两套 PCB 观测数据的器件与逐脚网络核对、摘要、分页查询和版本差异，保留完整原始输入。
• 增加完整关闭文件工程的隔离检查点与失败恢复，保留原工程和失败现场；验收后文件或证据变化时标记 STALE。
• 增加 G2-A 实测分区布局规划、写入前源数据核对、写入及重载后几何与属性对账。保留区内相对位置、两种原理图格式和无连线阶段。
• 补充官方 API 的布局执行流程、示例及中英文 README。
• 新增 27 项数据／恢复测试和 14 项布局测试通过；21 项既有 PCB 工具测试及导入器自检通过。

English

• Reconcile components and pin nets across observed PCB models; query summaries, pages and revision deltas while retaining full inputs.
• Add isolated checkpoints and failure recovery for complete closed-file projects. Preserve the source and failed work; mark changed accepted files/evidence STALE.
• Add measured G2-A block planning, source preflight and post-apply/reload geometry and property comparison. Preserve local positions, both schematic formats and the unwired stage.
• Document native execution through the official API, with examples and updated English/Chinese READMEs.
• All 27 new data/recovery and 14 layout tests passed, along with 21 existing PCB toolkit tests and the importer self-test.

范围 / Scope

布局规划器处理已完成区内摆放的无连线功能块。EDA 写入和真实保存重载需通过选定后端执行与验证。未实现实时 EDA 自动回滚；本次未验证真实 EDA 全流程、macOS、实板或 Token 节省比例。

The planner packs locally arranged unwired blocks. Native application and actual save/reload require the selected backend and separate verification. Live EDA rollback is not implemented. No live EDA end-to-end, macOS, physical board or token-saving benchmark is claimed for this release.

v1.5.0 · Engineering constraints & PCB inspection

v1.5.0 — 工程约束与独立 PCB 检查 / Engineering constraints and PCB inspection

中文

EDA 操作基础

• 内置 EasyEDA API 文档更新至 1.1.36，保留桥接窗口选择和状态检查修复。
• 集成官方原生格式文档、Schema 和离线校验依赖；新增按文档与图元类型校验的入口，拒绝不明确的回退。
• 增加社区 CLI/MCP 后端选择与交接说明。社区后端不自动安装，非商业许可实现不打包进入 MIT 项目。

独立检查与布线辅助

• 适配并内置 daishuge/pcb-skill 的脚本子集，保留 MIT 许可与来源记录。
• 增加受支持原生数据提取、布局与通道筛查、Gerber/钻孔/阻焊检查、三维包络检查和 DSN/SES 布线辅助入口。
• 修复未知网络误判通过、缺失封装被跳过、旧布线输出被当作任务完成等问题。
• 未支持的 Gerber 极性、变换和孔径宏明确报错；Windows 进程状态检查改为非终止式探测。

工程约束

• 将原厂依据、计算输入、EDA 规则、实际几何和制造文件复核对应到同一设计版本。
• 补充供电与启动、封装映射、时钟与回流、密脚扇出、热设计及逐项 DFM 警告处置。
• 新增阻焊开窗与阻焊桥、直线扇出通道、圆形孔环计算，以及中英文工程记录字段。
• 保留现有主流程、两种原理图格式和分阶段检查；默认交付范围仍为 G5 制造准备。

验证与适用范围

• 本次发布复测：81 项 Python 测试，80 项通过、1 项因 Windows 符号链接权限跳过；8 项 Node 格式校验测试通过，隔离的模拟桥接测试通过。
• 集成时的 21 个工具自测结果详见 VALIDATION.md。包内 MANIFEST.sha256.json 用于解压后的完整性检查。
• 原生导入仅覆盖所支持的数据格式。工具库板级模型与原有规范化快照仍是两个模型，需要同一基线下的交叉核对。
• 新工具链尚未完成真实 EDA 工程全流程、macOS、外部布线器互操作和实板制造验证。脚本通过不等于整板验收。

English

EDA operation foundations

• Update bundled EasyEDA API documentation to 1.1.36 while retaining bridge window-selection and health fixes.
• Bundle official native-format references, schemas and offline validator dependencies. Add explicit document/primitive dispatch without ambiguous schema fallback.
• Document optional community CLI/MCP backends and scoped handoffs. No automatic backend installation; the reviewed noncommercial implementation remains external.

Independent inspection and routing support

• Adapt the MIT-licensed script subset of daishuge/pcb-skill with attribution and provenance.
• Add supported native extraction, placement/channel screening, Gerber/drill/mask checks, mesh envelopes and DSN/SES helpers.
• Reject unresolved net assertions and missing footprints; prevent stale routing files from marking a new run complete.
• Fail explicitly on unsupported Gerber polarity, transforms and aperture macros. Probe Windows processes without terminating them.

Engineering constraints

• Connect exact-part/process sources, calculations, native rules, actual geometry and manufacturing review to one baseline.
• Expand power/startup, package mapping, clock/return, dense escape, thermal and item-specific DFM guidance.
• Add mask opening/web, straight escape-channel and circular annular-ring arithmetic plus English/Chinese project records.
• Preserve the workflow, two schematic formats and staged reviews. Default design delivery remains G5 manufacturing preparation.

Validation and scope

• Release rerun: 81 Python cases, 80 passed and one Windows symlink-permission skip; 8 Node format cases passed; isolated simulated bridge checks passed.
• Integration-time results for 21 toolkit self-tests are recorded in VALIDATION.md. MANIFEST.sha256.json verifies extracted package integrity.
• Native extraction has bounded format support. Toolkit board data and normalized snapshots remain separate models requiring same-baseline reconciliation.
• No new live EDA end-to-end, macOS, external-router interoperability or physical manufacturing validation is claimed.

v1.4.0 · Official schematic methods and design gates

官方操作能力与主流程集成

• 内置嘉立创官方原理图增强 Skill 1.2.0，与已有 easyeda-api 1.1.28 一起随包提供，无需额外安装前置 Skill。
• 明确分工：官方资料提供 EDA 连接、接口和具体操作方法；本项目负责从需求、选型、绘图到制造交付的主流程与验收要求。
• 新增原理图辅助方法库，涵盖功能分区框、批量选型与摆放、选择性网络引出、兼容探测、失败恢复和修改清理。保留上游来源、固定版本与许可声明。

绘图与检查改进

• 原理图限定为两种格式：自定义画布内的功能分区，或标准图框内部的功能分区。补充越界、标题栏占用、文字碰撞及可读性检查。
• 保留先摆放检查、后连线的两阶段流程。电源反馈、复位、BOOT 等关键局部电路要求清晰展示连接，避免全引脚标签化掩盖逻辑。
• 增加焊盘间、丝印间、丝印与阻焊开窗之间的几何筛查；同网焊盘和通孔跨层情况也纳入检查。工具使用规范化输入，不直接解析原生 EDA 文件，也不替代制造规则检查。
• 增加严格设计检查记录：器件真实规格、原理图格式与边界、布线准备、物理间距、发布冻结。缺项或不通过不能生成完整设计通过结论。
• 补充常见绘图问题的处理方法、有限次数修复和逐项警告处置。批量操作前验证单个对象；超时后先回读；删除前核对关联关系，避免重复创建和误删。

验证与升级

• 本次运行 50 项 Python 测试：49 项通过，1 项因 Windows 不允许创建符号链接而跳过。
• 主 Skill 与新增辅助 Skill 通过结构校验，102 处本地文档链接有效。完整安装包已独立解压并通过文件清单及 SHA-256 校验。
• 本次未进行连接 EDA 的实际绘图、原生 ERC/DRC 或实板测试。这些工具与记录校验不能证明某块板子的电气正确性。
• 升级时保留完整目录，包括两个 vendor 子目录。桥接代码本次未修改，无需仅因文档和方法库更新而重启正在运行的桥接。

English

Official operation layers and project workflow

• Bundles EasyEDA's schematic enhancement skill 1.2.0 alongside easyeda-api 1.1.28. No separate prerequisite skill installation is needed.
• Official references supply connection, API and operation recipes. PCB-Design-Skill retains responsibility for requirements, design sequencing, engineering review and manufacturing handoff.
• Adds an integrated methods reference for functional blocks, batch selection and placement, selective net fanout, compatibility probes, partial-failure recovery and ownership-aware cleanup.

Drawing and review improvements

• Requires either partitioned free-layout schematics or partitioned framed-layout schematics, with page-boundary, reserved-area and text-readability checks.
• Preserves placement review before wiring and readable direct connections for critical local circuits.
• Adds normalized geometry screening for pad-to-pad, silk-to-silk and silk-to-mask gaps, including same-net pads and through-hole layer coverage. This is not a native EDA parser or a substitute for manufacturing checks.
• Extends strict design evidence gates with part identity, routing readiness, visual/spacing checks and release freezing.
• Documents bounded repair, verified single-object edits before batches, readback after timeouts and scoped cleanup of obsolete objects.

Validation and upgrade

50 Python cases ran: 49 passed; one symbolic-link fixture was skipped due to Windows permissions. Skill structure and 102 local documentation links passed checks. The release archive was independently extracted and its manifest and SHA-256 hashes verified.

No live EDA drawing, native ERC/DRC or physical hardware validation was performed for this update. Keep the complete package, including both vendor directories. Bridge code is unchanged in this update.

v1.3.0 · Circuit intent and revision checks

电路检查与复用

• 新增关键引脚连接检查：同网、异网、完整节点成员及明确 NC，基于 EDA 实际导出数据核对独立编写的预期。
• 新增版本差异报告，列出器件增删、参数、封装、装配状态和引脚连接变化。
• 补充模块复用规范：接口、适用条件、独立命名、引脚复核和原生工程回读。
• 保留嘉立创EDA工作流、两阶段原理图、原生 ERC/DRC 和电气计算；无需 PCBDL 依赖。

Circuit intent and reuse

Added declared pin-relationship checks, component/pin revision comparison, and reusable-block guidance. The native EDA project remains authoritative for implemented design. All new code uses Python's standard library; no PCBDL source, runtime, exporters, or libraries are bundled.

Validation

41 Python tests passed, including 14 new data/CLI regression tests. Skill structure and 84 local Markdown links passed checks. An independent read-only review found no substantive defects within the declared scope. The release ZIP was independently extracted and verified.

These are data checks on synthetic fixtures. No live EDA extraction, native ERC/DRC, or hardware verification was performed. Checks cover declared pin relationships and component properties; actual power behavior, timing, impedance, placement, routing and board continuity require their corresponding engineering checks.

v1.2.1 · Schematic drafting standards

原理图规范

• 收录 8 项功能分区、信号/电源流向、外围元件与地回流规范，以及原始排版示例图。
• 原理图分为 G2-A 元件摆放与检查、G2-B 连线与电气审查。零连线要求仅适用于第一阶段快照，已有工程保留连接。
• 补充网络标签、连接点、NC 标记、接口针序、图页和可读性要求。
• 中英文模板新增 5 项原理图检查，总计 36 项；未加入固定最小封装尺寸限制。

Schematic drafting

• Includes eight organization rules and the supplied visual reference.
• Reviews component placement before wiring; preserves a scoped zero-wire snapshot. Existing wired designs retain their connections.
• Adds connectivity, annotation, page readability, and staged evidence requirements with matching English/Chinese templates.

Validation

27 Python tests and skill structure validation passed. Both language templates initialized successfully; local reference links and the independently extracted archive were checked. A read-only independent agent reviewed three drafting scenarios. No connected EDA drawing or macOS end-to-end validation was performed for this release.

The reference image has separate provenance and licensing notes in THIRD_PARTY_NOTICES.md.