v1.3.0 · Circuit intent and revision checks

电路检查与复用

• 新增关键引脚连接检查：同网、异网、完整节点成员及明确 NC，基于 EDA 实际导出数据核对独立编写的预期。
• 新增版本差异报告，列出器件增删、参数、封装、装配状态和引脚连接变化。
• 补充模块复用规范：接口、适用条件、独立命名、引脚复核和原生工程回读。
• 保留嘉立创EDA工作流、两阶段原理图、原生 ERC/DRC 和电气计算；无需 PCBDL 依赖。

Circuit intent and reuse

Added declared pin-relationship checks, component/pin revision comparison, and reusable-block guidance. The native EDA project remains authoritative for implemented design. All new code uses Python's standard library; no PCBDL source, runtime, exporters, or libraries are bundled.

Validation

41 Python tests passed, including 14 new data/CLI regression tests. Skill structure and 84 local Markdown links passed checks. An independent read-only review found no substantive defects within the declared scope. The release ZIP was independently extracted and verified.

These are data checks on synthetic fixtures. No live EDA extraction, native ERC/DRC, or hardware verification was performed. Checks cover declared pin relationships and component properties; actual power behavior, timing, impedance, placement, routing and board continuity require their corresponding engineering checks.