/ amaranth-soc Public
csr.periph: add Peripheral base class. #11
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This PR aims to add support for CSR-capable peripherals.
Related issue: #10
A new base class
csr.Peripheralcan be subclassed to provide nmigen-soc peripherals with helpers
for managing CSR registers and sending interrupt requests to a CPU. Support for interrupts is optional.
The plumbing (multiplexing the registers, managing events, requesting interrupts) between the peripheral and the outside world is done by the
PeripheralBridge, which is generated for the user by calling
self.csr_bridge(). It exposes a
csr.Interfaceand optionally an IRQ line. The bridge is an
Elaboratable, so the subclass must add it as a submodule during