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8 | 8 |
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9 | 9 | This library is distributed in the hope that it will be useful, |
10 | 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
11 | | - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
| 11 | + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
12 | 12 | See the GNU Lesser General Public License for more details. |
13 | 13 |
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14 | 14 | You should have received a copy of the GNU Lesser General Public |
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20 | 20 |
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21 | 21 | #if SAM3XA_SERIES |
22 | 22 |
|
| 23 | +void USBD_InitEndpoints(void) |
| 24 | +{ |
| 25 | +} |
| 26 | + |
| 27 | +uint32_t USBD_Init(void) |
| 28 | +{ |
| 29 | + uint32_t ul ; |
| 30 | + |
| 31 | + // Enables the USB Clock |
| 32 | + pmc_enable_periph_clk(ID_UOTGHS); |
| 33 | + pmc_enable_upll_clock(); |
| 34 | + pmc_switch_udpck_to_upllck(0); // div=0+1 |
| 35 | + pmc_enable_udpck(); |
| 36 | + |
| 37 | + // Configure interrupts |
| 38 | + NVIC_SetPriority((IRQn_Type) ID_UOTGHS, 0UL); |
| 39 | + NVIC_EnableIRQ((IRQn_Type) ID_UOTGHS); |
| 40 | + |
| 41 | + // Always authorize asynchrone USB interrupts to exit from sleep mode |
| 42 | + // for SAM3 USB wake up device except BACKUP mode |
| 43 | + pmc_set_fast_startup_input(PMC_FSMR_USBAL); |
| 44 | + |
| 45 | + // Enable USB macro |
| 46 | + UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_USBE; |
| 47 | + |
| 48 | + // Automatic mode speed for device |
| 49 | + UOTGHS->UOTGHS_DEVCTRL &= ~UOTGHS_DEVCTRL_SPDCONF_Msk; // Normal mode |
| 50 | + |
| 51 | + UOTGHS->UOTGHS_DEVCTRL &= ~( UOTGHS_DEVCTRL_LS | UOTGHS_DEVCTRL_TSTJ | UOTGHS_DEVCTRL_TSTK | |
| 52 | + UOTGHS_DEVCTRL_TSTPCKT | UOTGHS_DEVCTRL_OPMODE2 ); // Normal mode |
| 53 | + |
| 54 | + UOTGHS->UOTGHS_DEVCTRL = 0; |
| 55 | + UOTGHS->UOTGHS_HSTCTRL = 0; |
| 56 | + |
| 57 | + // Enable OTG pad |
| 58 | + UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_OTGPADE; |
| 59 | + |
| 60 | + // Enable clock OTG pad |
| 61 | + UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_FRZCLK; |
| 62 | + |
| 63 | + // Usb disable |
| 64 | + UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_USBE; |
| 65 | + UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_OTGPADE; |
| 66 | + UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_FRZCLK; |
| 67 | + |
| 68 | + // Usb enable |
| 69 | + UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_USBE; |
| 70 | + UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_OTGPADE; |
| 71 | + UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_FRZCLK; |
| 72 | + |
| 73 | + // Usb select_device |
| 74 | + UOTGHS->UOTGHS_CTRL &= ~UOTGHS_CTRL_UIDE; |
| 75 | + UOTGHS->UOTGHS_CTRL |= UOTGHS_CTRL_UIMOD_Device; |
| 76 | + |
| 77 | + // Device is in the Attached state |
| 78 | +// deviceState = USBD_STATE_SUSPENDED; |
| 79 | +// previousDeviceState = USBD_STATE_POWERED; |
| 80 | + |
| 81 | + // Enable USB macro and clear all other bits |
| 82 | + UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_CTRL_USBE; |
| 83 | + UOTGHS->UOTGHS_DEVCTRL = UOTGHS_CTRL_USBE; |
| 84 | + |
| 85 | + // Configure the pull-up on D+ and disconnect it |
| 86 | + USBD_Detach(); |
| 87 | + |
| 88 | + // Clear General IT |
| 89 | + UOTGHS->UOTGHS_SCR = (UOTGHS_SCR_IDTIC|UOTGHS_SCR_VBUSTIC|UOTGHS_SCR_SRPIC|UOTGHS_SCR_VBERRIC|UOTGHS_SCR_BCERRIC|UOTGHS_SCR_ROLEEXIC|UOTGHS_SCR_HNPERRIC|UOTGHS_SCR_STOIC|UOTGHS_SCR_VBUSRQC); |
| 90 | + |
| 91 | + // Clear OTG Device IT |
| 92 | + UOTGHS->UOTGHS_DEVICR = (UOTGHS_DEVICR_SUSPC|UOTGHS_DEVICR_MSOFC|UOTGHS_DEVICR_SOFC|UOTGHS_DEVICR_EORSTC|UOTGHS_DEVICR_WAKEUPC|UOTGHS_DEVICR_EORSMC|UOTGHS_DEVICR_UPRSMC); |
| 93 | + |
| 94 | + // Clear OTG Host IT |
| 95 | + UOTGHS->UOTGHS_HSTICR = (UOTGHS_HSTICR_DCONNIC|UOTGHS_HSTICR_DDISCIC|UOTGHS_HSTICR_RSTIC|UOTGHS_HSTICR_RSMEDIC|UOTGHS_HSTICR_RXRSMIC|UOTGHS_HSTICR_HSOFIC|UOTGHS_HSTICR_HWUPIC); |
| 96 | + |
| 97 | + // Reset all Endpoints Fifos |
| 98 | + UOTGHS->UOTGHS_DEVEPT |= (UOTGHS_DEVEPT_EPRST0|UOTGHS_DEVEPT_EPRST1|UOTGHS_DEVEPT_EPRST2|UOTGHS_DEVEPT_EPRST3|UOTGHS_DEVEPT_EPRST4| |
| 99 | + UOTGHS_DEVEPT_EPRST5|UOTGHS_DEVEPT_EPRST6|UOTGHS_DEVEPT_EPRST7|UOTGHS_DEVEPT_EPRST8); |
| 100 | + UOTGHS->UOTGHS_DEVEPT &= ~(UOTGHS_DEVEPT_EPRST0|UOTGHS_DEVEPT_EPRST1|UOTGHS_DEVEPT_EPRST2|UOTGHS_DEVEPT_EPRST3|UOTGHS_DEVEPT_EPRST4| |
| 101 | + UOTGHS_DEVEPT_EPRST5|UOTGHS_DEVEPT_EPRST6|UOTGHS_DEVEPT_EPRST7|UOTGHS_DEVEPT_EPRST8); |
| 102 | + |
| 103 | + // Disable all endpoints |
| 104 | + UOTGHS->UOTGHS_DEVEPT &= ~(UOTGHS_DEVEPT_EPEN0|UOTGHS_DEVEPT_EPEN1|UOTGHS_DEVEPT_EPEN2|UOTGHS_DEVEPT_EPEN3|UOTGHS_DEVEPT_EPEN4| |
| 105 | + UOTGHS_DEVEPT_EPEN5|UOTGHS_DEVEPT_EPEN6|UOTGHS_DEVEPT_EPEN7|UOTGHS_DEVEPT_EPEN8); |
| 106 | + |
| 107 | + // Device is in the Attached state |
| 108 | +// deviceState = USBD_STATE_SUSPENDED; |
| 109 | +// previousDeviceState = USBD_STATE_POWERED; |
| 110 | + |
| 111 | + // Automatic mode speed for device |
| 112 | + UOTGHS->UOTGHS_DEVCTRL &= ~UOTGHS_DEVCTRL_SPDCONF_Msk; |
| 113 | + // Force Full Speed mode for device |
| 114 | + //UOTGHS->UOTGHS_DEVCTRL = UOTGHS_DEVCTRL_SPDCONF_FORCED_FS; |
| 115 | + // Force High Speed mode for device |
| 116 | + //UOTGHS->UOTGHS_DEVCTRL = UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED; |
| 117 | + |
| 118 | + UOTGHS->UOTGHS_DEVCTRL &= ~(UOTGHS_DEVCTRL_LS|UOTGHS_DEVCTRL_TSTJ| UOTGHS_DEVCTRL_TSTK|UOTGHS_DEVCTRL_TSTPCKT|UOTGHS_DEVCTRL_OPMODE2) ; |
| 119 | + |
| 120 | + // Enable USB macro |
| 121 | + UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_CTRL_USBE; |
| 122 | + |
| 123 | + // Enable the UID pin select |
| 124 | + UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_CTRL_UIDE; |
| 125 | + |
| 126 | + // Enable OTG pad |
| 127 | + UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_CTRL_OTGPADE; |
| 128 | + |
| 129 | + // Enable clock OTG pad |
| 130 | + UOTGHS->UOTGHS_DEVCTRL &= ~UOTGHS_CTRL_FRZCLK; |
| 131 | + |
| 132 | + // With OR without DMA !!! |
| 133 | + // Initialization of DMA |
| 134 | + for( ul=1; ul<= UOTGHSDEVDMA_NUMBER ; ul++ ) |
| 135 | + { |
| 136 | + // RESET endpoint canal DMA: |
| 137 | + // DMA stop channel command |
| 138 | + UOTGHS->UOTGHS_DEVDMA[ul].UOTGHS_DEVDMACONTROL = 0; // STOP command |
| 139 | + |
| 140 | + // Disable endpoint |
| 141 | + UOTGHS->UOTGHS_DEVEPTIDR[ul] = (UOTGHS_DEVEPTIDR_TXINEC|UOTGHS_DEVEPTIDR_RXOUTEC|UOTGHS_DEVEPTIDR_RXSTPEC|UOTGHS_DEVEPTIDR_UNDERFEC|UOTGHS_DEVEPTIDR_NAKOUTEC| |
| 142 | + UOTGHS_DEVEPTIDR_HBISOINERREC|UOTGHS_DEVEPTIDR_NAKINEC|UOTGHS_DEVEPTIDR_HBISOFLUSHEC|UOTGHS_DEVEPTIDR_OVERFEC|UOTGHS_DEVEPTIDR_STALLEDEC| |
| 143 | + UOTGHS_DEVEPTIDR_CRCERREC|UOTGHS_DEVEPTIDR_SHORTPACKETEC|UOTGHS_DEVEPTIDR_MDATEC|UOTGHS_DEVEPTIDR_DATAXEC|UOTGHS_DEVEPTIDR_ERRORTRANSEC| |
| 144 | + UOTGHS_DEVEPTIDR_NBUSYBKEC|UOTGHS_DEVEPTIDR_FIFOCONC|UOTGHS_DEVEPTIDR_EPDISHDMAC|UOTGHS_DEVEPTIDR_NYETDISC|UOTGHS_DEVEPTIDR_STALLRQC); |
| 145 | + |
| 146 | + // Reset endpoint config |
| 147 | + UOTGHS->UOTGHS_DEVEPTCFG[ul] = 0UL; |
| 148 | + |
| 149 | + // Reset DMA channel (Buff count and Control field) |
| 150 | + UOTGHS->UOTGHS_DEVDMA[ul].UOTGHS_DEVDMACONTROL = 0x02UL; // NON STOP command |
| 151 | + |
| 152 | + // Reset DMA channel 0 (STOP) |
| 153 | + UOTGHS->UOTGHS_DEVDMA[ul].UOTGHS_DEVDMACONTROL = 0UL; // STOP command |
| 154 | + |
| 155 | + // Clear DMA channel status (read the register to clear it) |
| 156 | + UOTGHS->UOTGHS_DEVDMA[ul].UOTGHS_DEVDMASTATUS = UOTGHS->UOTGHS_DEVDMA[ul].UOTGHS_DEVDMASTATUS; |
| 157 | + } |
| 158 | + |
| 159 | + UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_CTRL_VBUSTE; |
| 160 | + UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_WAKEUPES; |
| 161 | + |
| 162 | + return 0UL ; |
| 163 | +} |
| 164 | + |
| 165 | +void USBD_Attach(void) |
| 166 | +{ |
| 167 | + UOTGHS->UOTGHS_DEVCTRL &= ~(unsigned int)UOTGHS_DEVCTRL_DETACH; |
| 168 | +} |
| 169 | + |
| 170 | +void USBD_Detach(void) |
| 171 | +{ |
| 172 | + UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_DEVCTRL_DETACH; |
| 173 | +} |
| 174 | + |
23 | 175 |
|
24 | 176 | #endif /* SAM3XA_SERIES */ |
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