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Description
current state:
the v2act -l <celllib.act> <verilog.v> assumes the cell lib to live inside namespace sync or async.
if the cells are in a different namespace they are reported as missing modules.
celllib.act :
namespace sync {
export defcell INVX1 (bool? A; bool! Y)
{
prs {
A => Y-
}
}
}
verilog.v
module blk1(in,out);
output [1:0] out;
input [1:0] in;
INVX1 cell1(.A (in[0]), .Y (out[0]));
INVX1 cell2(.A (in[1]), .Y (out[1]));
endmodule
output:
defproc blk1 (bool? in[2], bool! out[2])
{
/*--- types ---*/
INVX1 cell1;
INVX1 cell2;
/*--- connections ---*/
cell1(.A=in[0], .Y=out[0]);
cell1(.A=in[1], .Y=out[1]);
}
proposed behavior:
v2act -l <celllib.act> [-n namespace::subnamespace] with default to sync/async namespace
namespace::subnamespace can be any namespace hierarchy
namespace <namespace> {
namespace <subnamespace> {
export defcell INVX1 (bool? A; bool! Y)
{
prs {
A => Y-
}
}
}
}
verlig.v same as above
output:
defproc blk1 (bool? in[2], bool! out[2])
{
/*--- types ---*/
namespace::subnamespace::INVX1 cell1;
namespace::subnamespace::INVX1 cell2;
/*--- connections ---*/
cell1(.A=in[0], .Y=out[0]);
cell1(.A=in[1], .Y=out[1]);
}
purely optional (current use case does not need it):
have the ability to define multiple namespaces in which cells sit in.
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