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Merged
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Oct 25, 2025
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JIT: optimize shift right for platforms with 3 operands #1900

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184 changes: 92 additions & 92 deletions libs/jit/src/jit.erl
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22 changes: 19 additions & 3 deletions libs/jit/src/jit_aarch64.erl
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Original file line number Diff line number Diff line change
Expand Up @@ -983,13 +983,29 @@ merge_used_regs(State, []) ->
%% @param Shift number of bits to shift
%% @return new state
%%-----------------------------------------------------------------------------
-spec shift_right(state(), aarch64_register(), non_neg_integer()) -> state().
shift_right(#state{stream_module = StreamModule, stream = Stream0} = State, Reg, Shift) when
-spec shift_right(#state{}, maybe_free_aarch64_register(), non_neg_integer()) ->
{#state{}, aarch64_register()}.
shift_right(#state{stream_module = StreamModule, stream = Stream0} = State, {free, Reg}, Shift) when
?IS_GPR(Reg) andalso is_integer(Shift)
->
I = jit_aarch64_asm:lsr(Reg, Reg, Shift),
Stream1 = StreamModule:append(Stream0, I),
State#state{stream = Stream1}.
{State#state{stream = Stream1}, Reg};
shift_right(
#state{
stream_module = StreamModule,
stream = Stream0,
available_regs = [ResultReg | T],
used_regs = UR
} = State,
Reg,
Shift
) when
?IS_GPR(Reg) andalso is_integer(Shift)
->
I = jit_aarch64_asm:lsr(ResultReg, Reg, Shift),
Stream1 = StreamModule:append(Stream0, I),
{State#state{stream = Stream1, available_regs = T, used_regs = [ResultReg | UR]}, ResultReg}.

%%-----------------------------------------------------------------------------
%% @doc Emit a shift register left by a fixed number of bits, effectively
Expand Down
21 changes: 19 additions & 2 deletions libs/jit/src/jit_armv6m.erl
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Original file line number Diff line number Diff line change
Expand Up @@ -1381,12 +1381,29 @@ merge_used_regs(State, []) ->
%% @param Shift number of bits to shift
%% @return new state
%%-----------------------------------------------------------------------------
shift_right(#state{stream_module = StreamModule, stream = Stream0} = State, Reg, Shift) when
-spec shift_right(#state{}, maybe_free_armv6m_register(), non_neg_integer()) ->
{#state{}, armv6m_register()}.
shift_right(#state{stream_module = StreamModule, stream = Stream0} = State, {free, Reg}, Shift) when
?IS_GPR(Reg) andalso is_integer(Shift)
->
I = jit_armv6m_asm:lsrs(Reg, Reg, Shift),
Stream1 = StreamModule:append(Stream0, I),
State#state{stream = Stream1}.
{State#state{stream = Stream1}, Reg};
shift_right(
#state{
stream_module = StreamModule,
stream = Stream0,
available_regs = [ResultReg | T],
used_regs = UR
} = State,
Reg,
Shift
) when
?IS_GPR(Reg) andalso is_integer(Shift)
->
I = jit_armv6m_asm:lsrs(ResultReg, Reg, Shift),
Stream1 = StreamModule:append(Stream0, I),
{State#state{stream = Stream1, available_regs = T, used_regs = [ResultReg | UR]}, ResultReg}.

%%-----------------------------------------------------------------------------
%% @doc Emit a shift register left by a fixed number of bits, effectively
Expand Down
22 changes: 20 additions & 2 deletions libs/jit/src/jit_x86_64.erl
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Expand Up @@ -877,12 +877,30 @@ merge_used_regs(State, []) ->
%% @param Shift number of bits to shift
%% @return new state
%%-----------------------------------------------------------------------------
shift_right(#state{stream_module = StreamModule, stream = Stream0} = State, Reg, Shift) when
-spec shift_right(#state{}, maybe_free_x86_64_register(), non_neg_integer()) ->
{#state{}, x86_64_register()}.
shift_right(#state{stream_module = StreamModule, stream = Stream0} = State, {free, Reg}, Shift) when
?IS_GPR(Reg) andalso is_integer(Shift)
->
I = jit_x86_64_asm:shrq(Shift, Reg),
Stream1 = StreamModule:append(Stream0, I),
State#state{stream = Stream1}.
{State#state{stream = Stream1}, Reg};
shift_right(
#state{
stream_module = StreamModule,
available_regs = [ResultReg | T],
used_regs = UR,
stream = Stream0
} = State,
Reg,
Shift
) when
?IS_GPR(Reg) andalso is_integer(Shift)
->
I1 = jit_x86_64_asm:movq(Reg, ResultReg),
I2 = jit_x86_64_asm:shrq(Shift, ResultReg),
Stream1 = StreamModule:append(Stream0, <<I1/binary, I2/binary>>),
{State#state{stream = Stream1, available_regs = T, used_regs = [ResultReg | UR]}, ResultReg}.

%%-----------------------------------------------------------------------------
%% @doc Emit a shift register left by a fixed number of bits, effectively
Expand Down
39 changes: 28 additions & 11 deletions tests/libs/jit/jit_aarch64_tests.erl
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Expand Up @@ -760,17 +760,34 @@ if_else_block_test() ->
>>,
?assertEqual(dump_to_bin(Dump), Stream).

shift_right_test() ->
State0 = ?BACKEND:new(?JIT_VARIANT_PIC, jit_stream_binary, jit_stream_binary:new(0)),
{State1, Reg} = ?BACKEND:move_to_native_register(State0, {x_reg, 0}),
State2 = ?BACKEND:shift_right(State1, Reg, 3),
Stream = ?BACKEND:stream(State2),
Dump =
<<
" 0: f9401807 ldr x7, [x0, #48]\n"
" 4: d343fce7 lsr x7, x7, #3"
>>,
?assertEqual(dump_to_bin(Dump), Stream).
shift_right_test_() ->
[
?_test(begin
State0 = ?BACKEND:new(?JIT_VARIANT_PIC, jit_stream_binary, jit_stream_binary:new(0)),
{State1, Reg} = ?BACKEND:move_to_native_register(State0, {x_reg, 0}),
{State2, Reg} = ?BACKEND:shift_right(State1, {free, Reg}, 3),
Stream = ?BACKEND:stream(State2),
Dump =
<<
" 0: f9401807 ldr x7, [x0, #48]\n"
" 4: d343fce7 lsr x7, x7, #3"
>>,
?assertEqual(dump_to_bin(Dump), Stream)
end),
?_test(begin
State0 = ?BACKEND:new(?JIT_VARIANT_PIC, jit_stream_binary, jit_stream_binary:new(0)),
{State1, Reg} = ?BACKEND:move_to_native_register(State0, {x_reg, 0}),
{State2, OtherReg} = ?BACKEND:shift_right(State1, Reg, 3),
?assertNotEqual(OtherReg, Reg),
Stream = ?BACKEND:stream(State2),
Dump =
<<
" 0: f9401807 ldr x7, [x0, #48]\n"
" 4: d343fce8 lsr x8, x7, #3"
>>,
?assertEqual(dump_to_bin(Dump), Stream)
end)
].

shift_left_test() ->
State0 = ?BACKEND:new(?JIT_VARIANT_PIC, jit_stream_binary, jit_stream_binary:new(0)),
Expand Down
39 changes: 28 additions & 11 deletions tests/libs/jit/jit_armv6m_tests.erl
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Original file line number Diff line number Diff line change
Expand Up @@ -1183,17 +1183,34 @@ if_else_block_test() ->
>>,
?assertEqual(dump_to_bin(Dump), Stream).

shift_right_test() ->
State0 = ?BACKEND:new(?JIT_VARIANT_PIC, jit_stream_binary, jit_stream_binary:new(0)),
{State1, Reg} = ?BACKEND:move_to_native_register(State0, {x_reg, 0}),
State2 = ?BACKEND:shift_right(State1, Reg, 3),
Stream = ?BACKEND:stream(State2),
Dump =
<<
" 0: 6987 ldr r7, [r0, #24]\n"
" 2: 08ff lsrs r7, r7, #3"
>>,
?assertEqual(dump_to_bin(Dump), Stream).
shift_right_test_() ->
[
?_test(begin
State0 = ?BACKEND:new(?JIT_VARIANT_PIC, jit_stream_binary, jit_stream_binary:new(0)),
{State1, Reg} = ?BACKEND:move_to_native_register(State0, {x_reg, 0}),
{State2, Reg} = ?BACKEND:shift_right(State1, {free, Reg}, 3),
Stream = ?BACKEND:stream(State2),
Dump =
<<
" 0: 6987 ldr r7, [r0, #24]\n"
" 2: 08ff lsrs r7, r7, #3"
>>,
?assertEqual(dump_to_bin(Dump), Stream)
end),
?_test(begin
State0 = ?BACKEND:new(?JIT_VARIANT_PIC, jit_stream_binary, jit_stream_binary:new(0)),
{State1, Reg} = ?BACKEND:move_to_native_register(State0, {x_reg, 0}),
{State2, OtherReg} = ?BACKEND:shift_right(State1, Reg, 3),
?assertNotEqual(OtherReg, Reg),
Stream = ?BACKEND:stream(State2),
Dump =
<<
" 0: 6987 ldr r7, [r0, #24]\n"
" 2: 08fe lsrs r6, r7, #3"
>>,
?assertEqual(dump_to_bin(Dump), Stream)
end)
].

shift_left_test() ->
State0 = ?BACKEND:new(?JIT_VARIANT_PIC, jit_stream_binary, jit_stream_binary:new(0)),
Expand Down
40 changes: 29 additions & 11 deletions tests/libs/jit/jit_x86_64_tests.erl
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Original file line number Diff line number Diff line change
Expand Up @@ -820,17 +820,35 @@ if_else_block_test() ->
>>,
?assertEqual(dump_to_bin(Dump), Stream).

shift_right_test() ->
State0 = ?BACKEND:new(?JIT_VARIANT_PIC, jit_stream_binary, jit_stream_binary:new(0)),
{State1, Reg} = ?BACKEND:move_to_native_register(State0, {x_reg, 0}),
State2 = ?BACKEND:shift_right(State1, Reg, 3),
Stream = ?BACKEND:stream(State2),
Dump =
<<
" 0: 48 8b 47 30 mov 0x30(%rdi),%rax\n"
" 4: 48 c1 e8 03 shr $0x3,%rax"
>>,
?assertEqual(dump_to_bin(Dump), Stream).
shift_right_test_() ->
[
?_test(begin
State0 = ?BACKEND:new(?JIT_VARIANT_PIC, jit_stream_binary, jit_stream_binary:new(0)),
{State1, Reg} = ?BACKEND:move_to_native_register(State0, {x_reg, 0}),
{State2, Reg} = ?BACKEND:shift_right(State1, {free, Reg}, 3),
Stream = ?BACKEND:stream(State2),
Dump =
<<
" 0: 48 8b 47 30 mov 0x30(%rdi),%rax\n"
" 4: 48 c1 e8 03 shr $0x3,%rax"
>>,
?assertEqual(dump_to_bin(Dump), Stream)
end),
?_test(begin
State0 = ?BACKEND:new(?JIT_VARIANT_PIC, jit_stream_binary, jit_stream_binary:new(0)),
{State1, Reg} = ?BACKEND:move_to_native_register(State0, {x_reg, 0}),
{State2, OtherReg} = ?BACKEND:shift_right(State1, Reg, 3),
?assertNotEqual(OtherReg, Reg),
Stream = ?BACKEND:stream(State2),
Dump =
<<
" 0: 48 8b 47 30 mov 0x30(%rdi),%rax\n"
" 4: 49 89 c3 mov %rax,%r11\n"
" 7: 49 c1 eb 03 shr $0x3,%r11"
>>,
?assertEqual(dump_to_bin(Dump), Stream)
end)
].

shift_left_test() ->
State0 = ?BACKEND:new(?JIT_VARIANT_PIC, jit_stream_binary, jit_stream_binary:new(0)),
Expand Down
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