I typically don't upload school projects but this one was significant and unique enough to do so. This is a working single cycle MIPS Processor created from scratch in VHDL. It took about 3 months to do in a team of 3. It was benchmarked at around 45 mhz. Feel free to dig around through the files. Over 3 months of work, we never cleaned up the repo so it's a little messy. Enjoy!
Here is the high-level schmatic for the implementation:
