Kill is_minlevel & is_maxlevel from intrsource{}.

This is a step into turning intrsource{} MI and getting rid of the IPL
leftovers.

Author: haesbaert

sys/arch/amd64/amd64/acpi_machdep.c

@@ -251,13 +251,9 @@ acpi_sleep_clocks(struct acpi_softc *sc, int state)
 void
 acpi_resume_clocks(struct acpi_softc *sc)
 {
-	extern struct mutex intr_lock;
 #if NISA > 0
 	i8259_default_setup();
 #endif
-	mtx_enter(&intr_lock);
-	intr_calculatemasks(curcpu());
-	mtx_leave(&intr_lock);
 
 #if NIOAPIC > 0
 	ioapic_enable();

sys/arch/amd64/amd64/genassym.cf

@@ -122,7 +122,6 @@ member	is_pic
 member	is_flags
 member	is_pin
 member	is_type
-member	is_maxlevel
 
 struct	intrhand
 member	ih_fun

sys/arch/amd64/amd64/intr.c

@@ -132,62 +132,6 @@ x86_nmi(void)
 	return(0);
 }
 
-/*
- * Recalculate the interrupt masks from scratch.
- *
- * Must be called with intr_lock held.
- */
-void
-intr_calculatemasks(struct cpu_info *ci)
-{
-	int irq, level;
-	u_int64_t unusedirqs, intrlevel[MAX_INTR_SOURCES];
-	struct intrhand *q;
-
-	MUTEX_ASSERT_LOCKED(&intr_lock);
-
-	/* First, figure out which levels each IRQ uses. */
-	unusedirqs = 0xffffffffffffffffUL;
-	for (irq = 0; irq < MAX_INTR_SOURCES; irq++) {
-		int levels = 0;
-
-		if (ci->ci_isources[irq] == NULL) {
-			intrlevel[irq] = 0;
-			continue;
-		}
-		for (q = ci->ci_isources[irq]->is_handlers; q; q = q->ih_next)
-			levels |= (1 << q->ih_level);
-		intrlevel[irq] = levels;
-		if (levels)
-			unusedirqs &= ~(1UL << irq);
-	}
-
-	/* Then figure out which IRQs use each level. */
-	for (level = 0; level < NIPL; level++) {
-		u_int64_t irqs = 0;
-		for (irq = 0; irq < MAX_INTR_SOURCES; irq++)
-			if (intrlevel[irq] & (1 << level))
-				irqs |= (1UL << irq);
-	}
-
-	for (irq = 0; irq < MAX_INTR_SOURCES; irq++) {
-		int maxlevel = IPL_NONE;
-		int minlevel = IPL_HIGH;
-
-		if (ci->ci_isources[irq] == NULL)
-			continue;
-		for (q = ci->ci_isources[irq]->is_handlers; q;
-		     q = q->ih_next) {
-			if (q->ih_level < minlevel)
-				minlevel = q->ih_level;
-			if (q->ih_level > maxlevel)
-				maxlevel = q->ih_level;
-		}
-		ci->ci_isources[irq]->is_maxlevel = maxlevel;
-		ci->ci_isources[irq]->is_minlevel = minlevel;
-	}
-}
-
 /* 
  * Allocate an interrupt slot on the given cpu.
  * - Called with intr_lock held.
@@ -305,20 +249,10 @@ intr_allocate_slot(struct pic *pic, int legacy_irq, int pin, int level,
 duplicate:
 		if (pic == &i8259_pic)
 			idtvec = ICU_OFFSET + legacy_irq;
-		else {
-#ifdef IOAPIC_HWMASK
-			if (level > isp->is_maxlevel) {
-#else
-			if (isp->is_minlevel == 0 || level < isp->is_minlevel) {
-#endif
-				idtvec = idt_vec_alloc(APIC_LEVEL(level),
-				    IDT_INTR_HIGH);
-				if (idtvec == 0) {
-					return (EBUSY);
-				}
-			} else
-				idtvec = isp->is_idtvec;
-		}
+		else if (isp->is_idtvec == 0)
+			idtvec = idt_vec_alloc();
+		else
+			idtvec = isp->is_idtvec;
 	} else {
 other:
 		/*
@@ -342,7 +276,7 @@ intr_allocate_slot(struct pic *pic, int legacy_irq, int pin, int level,
 		}
 		return (EBUSY);
 found:
-		idtvec = idt_vec_alloc(APIC_LEVEL(level), IDT_INTR_HIGH);
+		idtvec = idt_vec_alloc();
 		if (idtvec == 0) {
 			free(ci->ci_isources[slot], M_DEVBUF);
 			ci->ci_isources[slot] = NULL;
@@ -474,9 +408,6 @@ intr_establish(int legacy_irq, struct pic *pic, int pin, int type, int level,
 
 	*p = ih;
 
-	intr_calculatemasks(ci);
-
-
 	if (source->is_idtvec != idt_vec) {
 		if (source->is_idtvec != 0 && source->is_idtvec != idt_vec)
 			idt_vec_free(source->is_idtvec);
@@ -541,7 +472,6 @@ intr_disestablish(struct intrhand *ih)
 
 	*p = q->ih_next;
 
-	intr_calculatemasks(ci);
 	if (source->is_handlers == NULL)
 		pic->pic_delroute(pic, ci, ih->ih_pin, idtvec, source->is_type);
 	else
@@ -594,7 +524,7 @@ intr_handler(struct intrframe *frame, struct intrhand *ih)
 
 /*
  * Fake interrupt handler structures for the benefit of symmetry with
- * other interrupt sources, and the benefit of intr_calculatemasks()
+ * other interrupt sources.
  */
 struct intrhand fake_softclock_intrhand;
 struct intrhand fake_softnet_intrhand;
@@ -635,9 +565,6 @@ cpu_intr_init(struct cpu_info *ci)
 	ci->ci_isources[LIR_TIMER] = isp;
 #endif
 
-	mtx_enter(&intr_lock);
-	intr_calculatemasks(ci);
-	mtx_leave(&intr_lock);
 }
 
 void
@@ -660,9 +587,9 @@ intr_printconfig(void)
 			isp = ci->ci_isources[i];
 			if (isp == NULL)
 				continue;
-			printf("cpu%u source %d is pin %d from pic %s maxlevel %d\n",
+			printf("cpu%u source %d is pin %d from pic %s\n",
 			    ci->ci_apicid, i, isp->is_pin,
-			    isp->is_pic->pic_name, isp->is_maxlevel);
+			    isp->is_pic->pic_name);
 			for (ih = isp->is_handlers; ih != NULL;
 			     ih = ih->ih_next)
 				printf("\thandler %p level %d\n",

sys/arch/amd64/amd64/machdep.c

@@ -1742,21 +1742,22 @@ need_resched(struct cpu_info *ci)
 }
 
 /*
- * Allocate an IDT vector slot within the given range.
+ * Allocate an IDT vector suitable for interrupts.
  * - only allocated from interrupt code, which is already locked
  */
 
 int
-idt_vec_alloc(int low, int high)
+idt_vec_alloc(void)
 {
 	int vec;
 
-	for (vec = low; vec <= high; vec++) {
+	for (vec = IDT_INTR_LOW; vec <= IDT_INTR_HIGH; vec++) {
 		if (idt_allocmap[vec] == 0) {
 			idt_allocmap[vec] = 1;
 			return vec;
 		}
 	}
+
 	return 0;
 }
 

sys/arch/amd64/include/intr.h

@@ -64,7 +64,6 @@ struct intrstub {
 };
 
 struct intrsource {
-	int is_maxlevel;		/* max. IPL for this source */
 	int is_pin;			/* IRQ for legacy; pin for IO APIC */
 	void (*is_run)(struct intrsource *);	/* Run callback to this source */
 	struct intrhand *is_handlers;	/* handler chain */
@@ -73,7 +72,6 @@ struct intrsource {
 	int is_flags;			/* see below */
 	int is_type;			/* level, edge */
 	int is_idtvec;
-	int is_minlevel;
 	volatile int is_scheduled;	/* proc is runnable */
 	struct proc *is_proc;		/* ithread proc */
 	TAILQ_ENTRY(intrsource) entry;	/* entry in ithreads list */
@@ -112,11 +110,6 @@ int spllower(int);
 int splraise(int);
 void softintr(int);
 
-/*
- * Convert spl level to local APIC level
- */
-#define APIC_LEVEL(l)   ((l) << 4)
-
 /*
  * compiler barrier: prevent reordering of instructions.
  * XXX something similar will move to <sys/cdefs.h>

sys/arch/amd64/include/segments.h

@@ -163,7 +163,7 @@ void set_sys_segment(struct sys_segment_descriptor *, void *, size_t,
 			  int, int, int);
 void set_mem_segment(struct mem_segment_descriptor *, void *, size_t,
 			  int, int, int, int, int);
-int idt_vec_alloc(int, int);
+int idt_vec_alloc(void);
 void idt_vec_set(int, void (*)(void));
 void idt_vec_free(int);
 void cpu_init_idt(void);

sys/kern/kern_ithread.c

@@ -101,9 +101,6 @@ ithread(void *v_is)
 void
 ithread_run(struct intrsource *is)
 {
-#ifdef ITHREAD_DEBUG
-	struct cpu_info *ci = curcpu();
-#endif
 	struct proc *p = is->is_proc;
 
 	if (p == NULL) {
@@ -113,9 +110,7 @@ ithread_run(struct intrsource *is)
 		return;
 	}
 
-	DPRINTF(10, "ithread accepted interrupt pin %d "
-	    "(ilevel = %d, maxlevel = %d)\n",
-	    is->is_pin, ci->ci_ilevel, is->is_maxlevel);
+	DPRINTF(10, "ithread accepted interrupt pin %d\n", is->is_pin);
 
 	SCHED_LOCK();		/* implies crit_enter() ! */
 
@@ -225,7 +220,6 @@ ithread_softregister(int level, int (*handler)(void *), void *arg, int flags)
 
 	is->is_type = IST_LEVEL; /* XXX more like level than EDGE */
 	is->is_pic = &softintr_pic;
-	is->is_minlevel = IPL_HIGH;
 
 	ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT | M_ZERO);
 	if (ih == NULL)
@@ -242,11 +236,6 @@ ithread_softregister(int level, int (*handler)(void *), void *arg, int flags)
 	ih->ih_next = is->is_handlers;
 	is->is_handlers = ih;
 
-	if (ih->ih_level > is->is_maxlevel)
-		is->is_maxlevel = ih->ih_level;
-	if (ih->ih_level < is->is_minlevel) /* XXX minlevel will be gone */
-		is->is_minlevel = ih->ih_level;
-
 	ithread_register(is);
 
 	return (is);