arm: improve imxpcibr so that we finally have PCI

Lots of various kinds of changes to improve the driver.

Add a hook into arm's fault code, so that we can tell
it to ignore the abort caused by the PCIe controller.

Author: bluerise

sys/arch/arm/arm/fault.c

@@ -132,8 +132,10 @@ static int dab_align(trapframe_t *, u_int, u_int, struct proc *,
     struct sigdata *sd);
 static int dab_buserr(trapframe_t *, u_int, u_int, struct proc *,
     struct sigdata *sd);
+void data_fault_hook(int code, int (*func)(trapframe_t *, u_int, u_int,
+    struct proc *, struct sigdata *));
 
-static const struct data_abort data_aborts[] = {
+static struct data_abort data_aborts[] = {
 	{dab_fatal,	"V7 fault 00000"},
 	{dab_align,	"Alignment Fault 1"},
 	{dab_fatal,	"Debug Event"},
@@ -370,6 +372,15 @@ data_abort_handler(trapframe_t *tf)
 		userret(p);
 }
 
+void
+data_fault_hook(int code, int (*func)(trapframe_t *, u_int, u_int,
+    struct proc *, struct sigdata *))
+{
+	if (code >= nitems(data_aborts))
+		return;
+	data_aborts[code].func = func;
+}
+
 /*
  * dab_fatal() handles the following data aborts:
  *

sys/arch/armv7/conf/generic.imx

@@ -22,8 +22,12 @@ imxuart*	at fdt?			# onboard uarts
 imxiic*		at imx?			# i2c
 imxiic*		at fdt?			# i2c
 
-#imxpcibr*	at imx?			# PCIe controller host bridge
-#pci*		at imxpcibr?
+imxpcibr*	at imx?			# PCIe controller host bridge
+pci*		at imxpcibr?
+ppb*		at pci?			# PCI-PCI bridges
+pci*		at ppb?
+em*		at pci?
+iwn*		at pci?
 
 imxahci*	at imx?			# AHCI/SATA
 ahci*		at imxahci?		# AHCI/SATA

sys/arch/armv7/imx/files.imx

@@ -84,8 +84,8 @@ attach	maxgpio at i2c
 file	arch/armv7/imx/maxim7301.c		maxgpio
 
 # PCI
-#include "dev/pci/files.pci"
+include "dev/pci/files.pci"
 
-#device	imxpcibr {} : pcibus
-#attach	imxpcibr at imx
-#file	arch/armv7/imx/imxpcibr.c		imxpcibr
+device	imxpcibr {} : pcibus
+attach	imxpcibr at imx
+file	arch/armv7/imx/imxpcibr.c		imxpcibr

sys/arch/armv7/imx/imx.c

@@ -91,6 +91,7 @@ struct board_dev sabrelite_devs[] = {
 	{ "imxgpio",	4 },
 	{ "imxgpio",	5 },
 	{ "imxgpio",	6 },
+	{ "imxpcibr",	0 },
 	{ "imxesdhc",	2 },
 	{ "imxesdhc",	3 },
 	{ "imxehci",	0 },
@@ -136,6 +137,7 @@ struct board_dev utilite_devs[] = {
 	{ "imxgpio",	5 },
 	{ "imxgpio",	6 },
 	{ "imxiic",	2 },
+	{ "imxpcibr",	0 },
 	{ "imxesdhc",	2 },
 	{ "imxehci",	0 },
 	{ "imxenet",	0 },

sys/arch/armv7/imx/imx6.c

@@ -143,6 +143,10 @@
 #define PCIE_REG_SIZE	0x4000
 #define PCIE_MAP_ADDR	0x01000000
 #define PCIE_MAP_SIZE	0xffc000
+#define PCIE_IO_ADDR	0x01f80000
+#define PCIE_IO_SIZE	0x00010000
+#define PCIE_MEM_ADDR	0x01000000
+#define PCIE_MEM_SIZE	0x00f00000
 
 #define PCIE_IRQ0	120
 #define PCIE_IRQ1	121
@@ -360,7 +364,8 @@ struct armv7_dev imx6_devs[] = {
 	  .unit = 0,
 	  .mem = {
 		  { PCIE_REG_ADDR, PCIE_REG_SIZE },
-		  { PCIE_MAP_ADDR, PCIE_MAP_SIZE },
+		  { PCIE_IO_ADDR, PCIE_IO_SIZE },
+		  { PCIE_MEM_ADDR, PCIE_MEM_SIZE },
 	  },
 	  .irq = { PCIE_IRQ0, PCIE_IRQ1, PCIE_IRQ1, PCIE_IRQ2 }
 	},

sys/arch/armv7/imx/imxccm.c

@@ -158,9 +158,8 @@ enum clocks {
 };
 
 static const char *axi_sels[]		= { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
-static const char *lvds_sels[]		= { "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
-					    "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
-					    "pcie_ref", "sata_ref", };
+static const char *lvds_sels[]		= { "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy",
+					    "dummy", "dummy", "dummy", "pcie_ref", "sata_ref", "usbphy1", "usbphy2", };
 static const char *periph_pre_sels[]	= { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
 static const char *periph_clk2_sels[]	= { "pll3_usb_otg", "osc", "osc", "dummy", };
 static const char *periph2_clk2_sels[]	= { "pll3_usb_otg", "pll2_bus", };
@@ -346,6 +345,8 @@ imxccm_attach(struct device *parent, struct device *self, void *args)
 
 	/* usb */
 	imxccm_gate2("usboh3", "ipg", CCM_CCGR6, 0);
+	imxccm_gate("usbphy1", "pll3_usb_otg", CCM_ANALOG_PLL_USB1, 20);
+	imxccm_gate("usbphy2", "pll7_usb_host", CCM_ANALOG_PLL_USB2, 20);
 	imxccm_gate("usbphy1_gate", "dummy", CCM_ANALOG_PLL_USB1, 6);
 	imxccm_gate("usbphy2_gate", "dummy", CCM_ANALOG_PLL_USB2, 6);
 
@@ -359,12 +360,13 @@ imxccm_attach(struct device *parent, struct device *self, void *args)
 	imxccm_gate2("pcie_axi", "pcie_axi_sel", CCM_CCGR4, 0);
 	clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
 	imxccm_gate("pcie_ref_125m", "pcie_ref", CCM_ANALOG_PLL_ENET, 19);
+	clk_set_parent(clk_get("pcie_axi_sel"), clk_get("axi"));
 
 	/* lvds */
 	imxccm_mux("lvds1_sel", CCM_PMU_MISC1, 0, 5, lvds_sels, nitems(lvds_sels));
 	imxccm_mux("lvds2_sel", CCM_PMU_MISC1, 5, 5, lvds_sels, nitems(lvds_sels));
-	imxccm_gate("lvds1_gate", "dummy", CCM_PMU_MISC1, 10);
-	imxccm_gate("lvds2_gate", "dummy", CCM_PMU_MISC1, 11);
+	imxccm_gate("lvds1_out", "lvds1_sel", CCM_PMU_MISC1, 10);
+	imxccm_gate("lvds2_out", "lvds1_sel", CCM_PMU_MISC1, 11);
 	clk_set_parent(clk_get("lvds1_sel"), clk_get("sata_ref")); /* PCIe */
 
 	cpu_type = HREAD4(sc, CCM_ANALOG_DIGPROG_MX6SL);

sys/arch/armv7/imx/imxiomuxc.c

@@ -69,8 +69,8 @@
 #define IOMUXC_GPR12_APPS_PM_XMT_PME				(1 << 9)
 #define IOMUXC_GPR12_APPS_LTSSM_ENABLE				(1 << 10)
 #define IOMUXC_GPR12_APPS_INIT_RST				(1 << 11)
-#define IOMUXC_GPR12_DEVICE_TYPE_RC				(2 << 12)
-#define IOMUXC_GPR12_DEVICE_TYPE_MASK				(3 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_RC				(4 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_MASK				(0xf << 12)
 #define IOMUXC_GPR12_APPS_PM_XMT_TURNOFF			(1 << 16)
 
 #define IOMUXC_GPR13_SATA_PHY_1_FAST_EDGE_RATE			(0x00 << 0)