Use the intr_ as prefix for interrupt API, intr_[disable|enable|...]

haesbaert · haesbaert · commit b9652d2b3bf0 · 2015-01-16T12:26:15.000+01:00
Discussed with Patrick, we both agree this makes more sense than using
a suffix.

Also use intr_get_state() and intr_set_state() instead of state() and
restore().
diff --git a/sys/arch/amd64/amd64/amd64_mem.c b/sys/arch/amd64/amd64/amd64_mem.c
@@ -275,12 +275,12 @@ mrt2mtrr(u_int64_t flags)
 void
 mrstore(struct mem_range_softc *sc)
 {
-	disable_intr();				/* disable interrupts */
+	intr_disable();				/* disable interrupts */
 #ifdef MULTIPROCESSOR
 	x86_broadcast_ipi(X86_IPI_MTRR);
 #endif
 	mrstoreone(sc);
-	enable_intr();
+	intr_enable();
 }
 
 /*
@@ -617,7 +617,7 @@ mrinit_cpu(struct mem_range_softc *sc)
 void
 mrreload_cpu(struct mem_range_softc *sc)
 {
-	disable_intr();
+	intr_disable();
 	mrstoreone(sc); /* set MTRRs to match BSP */
-	enable_intr();
+	intr_enable();
 }
diff --git a/sys/arch/amd64/amd64/hibernate_machdep.c b/sys/arch/amd64/amd64/hibernate_machdep.c
@@ -411,13 +411,13 @@ hibernate_inflate_skip(union hibernate_info *hib_info, paddr_t dest)
 void
 hibernate_enable_intr_machdep(void)
 {
-	enable_intr();
+	intr_enable();
 }
 
 void
 hibernate_disable_intr_machdep(void)
 {
-	disable_intr();
+	intr_disable();
 }
 
 #ifdef MULTIPROCESSOR
diff --git a/sys/arch/amd64/amd64/i8259.c b/sys/arch/amd64/amd64/i8259.c
@@ -168,7 +168,7 @@ i8259_hwunmask(struct pic *pic, int pin)
 	unsigned port;
 	u_int8_t byte;
 
-	disable_intr();	/* XXX */
+	intr_disable();	/* XXX */
 	i8259_imen &= ~(1 << pin);
 #ifdef PIC_MASKDELAY
 	delay(10);
@@ -181,7 +181,7 @@ i8259_hwunmask(struct pic *pic, int pin)
 		byte = i8259_imen & 0xff;
 	}
 	outb(port, byte);
-	enable_intr();
+	intr_enable();
 }
 
 static void
diff --git a/sys/arch/amd64/amd64/ioapic.c b/sys/arch/amd64/amd64/ioapic.c
@@ -116,7 +116,7 @@ ioapic_lock(struct ioapic_softc *sc)
 	u_long flags;
 
 	flags = read_psl();
-	disable_intr();
+	intr_disable();
 #ifdef MULTIPROCESSOR
 	mtx_enter(&sc->sc_pic.pic_mutex);
 #endif
diff --git a/sys/arch/amd64/amd64/ipifuncs.c b/sys/arch/amd64/amd64/ipifuncs.c
@@ -100,7 +100,7 @@ x86_64_ipi_halt(struct cpu_info *ci)
 	KASSERT(!__mp_lock_held(&kernel_lock));
 	
 	fpusave_cpu(ci, 1);
-	disable_intr();
+	intr_disable();
 	lapic_disable();
 	wbinvd();
 	ci->ci_flags &= ~CPUF_RUNNING;
diff --git a/sys/arch/amd64/amd64/lapic.c b/sys/arch/amd64/amd64/lapic.c
@@ -97,7 +97,7 @@ lapic_map(paddr_t lapic_base)
 	pt_entry_t *pte;
 	vaddr_t va = (vaddr_t)&local_apic;
 
-	disable_intr();
+	intr_disable();
 	s = lapic_tpr;
 
 	/*
@@ -114,7 +114,7 @@ lapic_map(paddr_t lapic_base)
 	invlpg(va);
 
 	lapic_tpr = s;
-	enable_intr();
+	intr_enable();
 }
 
 /*
@@ -358,7 +358,7 @@ lapic_calibrate_timer(struct cpu_info *ci)
 	i82489_writereg(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1);
 	i82489_writereg(LAPIC_ICR_TIMER, 0x80000000);
 
-	disable_intr();
+	intr_disable();
 
 	/* wait for current cycle to finish */
 	wait_next_cycle();
diff --git a/sys/arch/amd64/amd64/lock_machdep.c b/sys/arch/amd64/amd64/lock_machdep.c
@@ -80,7 +80,7 @@ __mp_lock(struct __mp_lock *mpl)
 	long rf = read_rflags();
 	struct __mp_lock_cpu *cpu = &mpl->mpl_cpus[cpu_number()];
 
-	disable_intr();
+	intr_disable();
 	if (cpu->mplc_depth++ == 0)
 		cpu->mplc_ticket = fetch_and_add(&mpl->mpl_users, 1);
 	write_rflags(rf);
@@ -101,7 +101,7 @@ __mp_unlock(struct __mp_lock *mpl)
 	}
 #endif
 
-	disable_intr();	
+	intr_disable();
 	if (--cpu->mplc_depth == 0)
 		mpl->mpl_ticket++;
 	write_rflags(rf);
@@ -114,7 +114,7 @@ __mp_release_all(struct __mp_lock *mpl)
 	int rv = cpu->mplc_depth;
 	long rf = read_rflags();
 
-	disable_intr();
+	intr_disable();
 	cpu->mplc_depth = 0;
 	mpl->mpl_ticket++;
 	write_rflags(rf);
diff --git a/sys/arch/amd64/amd64/machdep.c b/sys/arch/amd64/amd64/machdep.c
@@ -1585,7 +1585,7 @@ init_x86_64(paddr_t first_avail)
 	fpuinit(&cpu_info_primary);
 
 	crit_enter();		/* XXX need to think this through */
-	enable_intr();
+	intr_enable();
 
 #ifdef DDB
 	db_machine_init();
@@ -1620,7 +1620,7 @@ void
 cpu_reset(void)
 {
 
-	disable_intr();
+	intr_disable();
 
 	if (cpuresetfn)
 		(*cpuresetfn)();
diff --git a/sys/arch/amd64/include/cpufunc.h b/sys/arch/amd64/include/cpufunc.h
@@ -193,13 +193,13 @@ void	setidt(int idx, /*XXX*/caddr_t func, int typ, int dpl);
 typedef u_long intr_state_t;
 
 static __inline void
-disable_intr(void)
+intr_disable(void)
 {
 	__asm volatile("cli");
 }
 
 static __inline void
-enable_intr(void)
+intr_enable(void)
 {
 	__asm volatile("sti");
 }
@@ -219,8 +219,8 @@ write_rflags(u_long ef)
 	__asm volatile("pushq %0; popfq" : : "r" (ef));
 }
 
-#define state_intr read_rflags
-#define restore_intr write_rflags
+#define intr_get_state read_rflags
+#define intr_set_state write_rflags
 
 static __inline u_int64_t
 rdmsr(u_int msr)
diff --git a/sys/arch/amd64/isa/clock.c b/sys/arch/amd64/isa/clock.c
@@ -217,7 +217,7 @@ gettick(void)
 	/* Don't want someone screwing with the counter while we're here. */
 	mtx_enter(&timer_mutex);
 	ef = read_rflags();
-	disable_intr();
+	intr_disable();
 	/* Select counter 0 and latch it. */
 	outb(IO_TIMER1+TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
 	lo = inb(IO_TIMER1+TIMER_CNTR0);
@@ -662,7 +662,7 @@ i8254_get_timecount(struct timecounter *tc)
 	u_long ef;
 
 	ef = read_rflags();
-	disable_intr();
+	intr_disable();
 
 	outb(IO_TIMER1+TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
 	lo = inb(IO_TIMER1+TIMER_CNTR0);
diff --git a/sys/dev/acpi/acpi.c b/sys/dev/acpi/acpi.c
@@ -1984,7 +1984,7 @@ acpi_sleep_pm(struct acpi_softc *sc, int state)
 	uint16_t rega, regb, regra, regrb;
 	int retry = 0;
 
-	disable_intr();
+	intr_disable();
 
 	/* Clear WAK_STS bit */
 	acpi_write_pmreg(sc, ACPIREG_PM1_STS, 0, ACPI_PM1_WAK_STS);
@@ -2148,7 +2148,7 @@ acpi_sleep_state(struct acpi_softc *sc, int state)
 	resettodr();
 
 	crit_enter();
-	disable_intr();	/* PSL_I for resume; PIC/APIC broken until repair */
+	intr_disable();	/* PSL_I for resume; PIC/APIC broken until repair */
 	cold = 1;	/* Force other code to delay() instead of tsleep() */
 
 	if (config_suspend_all(DVACT_SUSPEND) != 0)
@@ -2196,7 +2196,7 @@ acpi_sleep_state(struct acpi_softc *sc, int state)
 
 fail_suspend:
 	cold = 0;
-	enable_intr();
+	intr_enable();
 	crit_leave();
 
 	acpibtn_disable_psw();		/* disable _LID for wakeup */
@@ -2268,7 +2268,7 @@ acpi_powerdown(void)
 		return;
 
 	crit_enter();
-	disable_intr();
+	intr_disable();
 	cold = 1;
 
 	/* 1st powerdown AML step: _PTS(tostate) */
diff --git a/sys/dev/isa/gus.c b/sys/dev/isa/gus.c
@@ -3336,7 +3336,7 @@ gus_subattach(struct gus_softc *sc, struct isa_attach_args *ia)
 	 * The order of these operations is very magical.
 	 */
 
-	disable_intr();		/* XXX needed? */
+	intr_disable();		/* XXX needed? */
 
 	bus_space_write_1(iot, sc->sc_ioh1, GUS_REG_CONTROL, GUS_REG_IRQCTL);
 	bus_space_write_1(iot, sc->sc_ioh1, GUS_MIX_CONTROL, m);
@@ -3366,7 +3366,7 @@ gus_subattach(struct gus_softc *sc, struct isa_attach_args *ia)
 	     (m | GUSMASK_LATCHES) & ~(GUSMASK_LINE_OUT|GUSMASK_LINE_IN));
 	bus_space_write_1(iot, sc->sc_ioh2, GUS_VOICE_SELECT, 0x00);
 
-	enable_intr();
+	intr_enable();
 
 	sc->sc_mixcontrol =
 		(m | GUSMASK_LATCHES) & ~(GUSMASK_LINE_OUT|GUSMASK_LINE_IN);
diff --git a/sys/kern/kern_crit.c b/sys/kern/kern_crit.c
@@ -86,18 +86,18 @@ crit_rundeferred(void)
 
 	KASSERT(CRIT_DEPTH == 0);
 
-	ist = state_intr();
-	disable_intr();
+	ist = intr_get_state();
+	intr_disable();
 
 	ci->ci_idepth++;
 	while (ci->ci_ipending) {
 		/* XXX can be optimized by having a btrq based flsq */
 		i = IPENDING_NEXT(ci);
 		IPENDING_CLR(ci, i);
-		enable_intr();
+		intr_enable();
 		ci->ci_isources[i]->is_run(ci->ci_isources[i]);
-		disable_intr();
+		intr_disable();
 	}
 	ci->ci_idepth--;
-	restore_intr(ist);
+	intr_set_state(ist);
 }
diff --git a/sys/kern/kern_sched.c b/sys/kern/kern_sched.c
@@ -145,7 +145,7 @@ sched_idle(void *v)
 	KASSERT(curproc == spc->spc_idleproc);
 
 	/* Now we have a full-blown process, we can enable interrupts */
-	enable_intr();
+	intr_enable();
 
 	while (1) {
 		while (!curcpu_is_idle()) {

Original file line number	Diff line number	Diff line change
`@@ -275,12 +275,12 @@ mrt2mtrr(u_int64_t flags)`
`275`	`275`	`void`
`276`	`276`	`mrstore(struct mem_range_softc *sc)`
`277`	`277`	`{`
`278`		`- disable_intr(); /* disable interrupts */`
	`278`	`+ intr_disable(); /* disable interrupts */`
`279`	`279`	`#ifdef MULTIPROCESSOR`
`280`	`280`	`x86_broadcast_ipi(X86_IPI_MTRR);`
`281`	`281`	`#endif`
`282`	`282`	`mrstoreone(sc);`
`283`		`- enable_intr();`
	`283`	`+ intr_enable();`
`284`	`284`	`}`
`285`	`285`
`286`	`286`	`/*`
`@@ -617,7 +617,7 @@ mrinit_cpu(struct mem_range_softc *sc)`
`617`	`617`	`void`
`618`	`618`	`mrreload_cpu(struct mem_range_softc *sc)`
`619`	`619`	`{`
`620`		`- disable_intr();`
	`620`	`+ intr_disable();`
`621`	`621`	`mrstoreone(sc); /* set MTRRs to match BSP */`
`622`		`- enable_intr();`
	`622`	`+ intr_enable();`
`623`	`623`	`}`
Original file line number	Diff line number	Diff line change
`@@ -411,13 +411,13 @@ hibernate_inflate_skip(union hibernate_info *hib_info, paddr_t dest)`
`411`	`411`	`void`
`412`	`412`	`hibernate_enable_intr_machdep(void)`
`413`	`413`	`{`
`414`		`- enable_intr();`
	`414`	`+ intr_enable();`
`415`	`415`	`}`
`416`	`416`
`417`	`417`	`void`
`418`	`418`	`hibernate_disable_intr_machdep(void)`
`419`	`419`	`{`
`420`		`- disable_intr();`
	`420`	`+ intr_disable();`
`421`	`421`	`}`
`422`	`422`
`423`	`423`	`#ifdef MULTIPROCESSOR`
Original file line number	Diff line number	Diff line change
`@@ -193,13 +193,13 @@ void setidt(int idx, /XXX/caddr_t func, int typ, int dpl);`
`193`	`193`	`typedef u_long intr_state_t;`
`194`	`194`
`195`	`195`	`static __inline void`
`196`		`-disable_intr(void)`
	`196`	`+intr_disable(void)`
`197`	`197`	`{`
`198`	`198`	`__asm volatile("cli");`
`199`	`199`	`}`
`200`	`200`
`201`	`201`	`static __inline void`
`202`		`-enable_intr(void)`
	`202`	`+intr_enable(void)`
`203`	`203`	`{`
`204`	`204`	`__asm volatile("sti");`
`205`	`205`	`}`
`@@ -219,8 +219,8 @@ write_rflags(u_long ef)`
`219`	`219`	`__asm volatile("pushq %0; popfq" : : "r" (ef));`
`220`	`220`	`}`
`221`	`221`
`222`		`-#define state_intr read_rflags`
`223`		`-#define restore_intr write_rflags`
	`222`	`+#define intr_get_state read_rflags`
	`223`	`+#define intr_set_state write_rflags`
`224`	`224`
`225`	`225`	`static __inline u_int64_t`
`226`	`226`	`rdmsr(u_int msr)`