Skip to content

Commit c87c5bd

Browse files
bluerisebluerise
committed
arm: add support for Marvell's PJ4B
From NetBSD.
1 parent a0a1a6c commit c87c5bd

File tree

6 files changed

+228
-4
lines changed

6 files changed

+228
-4
lines changed

‎sys/arch/arm/arm/cpu.c‎

Lines changed: 21 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,8 @@ cpu_attach(struct device *dv)
8686

8787
enum cpu_class {
8888
CPU_CLASS_NONE,
89-
CPU_CLASS_ARMv7
89+
CPU_CLASS_ARMv7,
90+
CPU_CLASS_PJ4B
9091
};
9192

9293
static const char * const generic_steppings[16] = {
@@ -137,6 +138,21 @@ const struct cpuidtab cpuids[] = {
137138
{ CPU_ID_CORTEX_A15_R4, CPU_CLASS_ARMv7, "ARM Cortex A15 R4",
138139
generic_steppings },
139140

141+
{ CPU_ID_MV88SV581X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV581x",
142+
generic_steppings },
143+
{ CPU_ID_ARM_88SV581X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV581x",
144+
generic_steppings },
145+
{ CPU_ID_MV88SV581X_V7, CPU_CLASS_PJ4B, "Sheeva 88SV581x",
146+
generic_steppings },
147+
{ CPU_ID_ARM_88SV581X_V7, CPU_CLASS_PJ4B, "Sheeva 88SV581x",
148+
generic_steppings },
149+
{ CPU_ID_MV88SV584X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV584x",
150+
generic_steppings },
151+
{ CPU_ID_ARM_88SV584X_V6, CPU_CLASS_PJ4B, "Sheeva 88SV584x",
152+
generic_steppings },
153+
{ CPU_ID_MV88SV584X_V7, CPU_CLASS_PJ4B, "Sheeva 88SV584x",
154+
generic_steppings },
155+
140156
{ 0, CPU_CLASS_NONE, NULL, NULL }
141157
};
142158

@@ -147,8 +163,8 @@ struct cpu_classtab {
147163

148164
const struct cpu_classtab cpu_classes[] = {
149165
{ "unknown", NULL }, /* CPU_CLASS_NONE */
150-
{ "ARMv7", "CPU_ARMv7" } /* CPU_CLASS_ARMv7 */
151-
166+
{ "ARMv7", "CPU_ARMv7" }, /* CPU_CLASS_ARMv7 */
167+
{ "Marvell", "CPU_PJ4B" }, /* CPU_CLASS_PJ4B */
152168
};
153169

154170
/*
@@ -211,6 +227,7 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci)
211227

212228
switch (cpu_class) {
213229
case CPU_CLASS_ARMv7:
230+
case CPU_CLASS_PJ4B:
214231
if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0)
215232
printf(" DC disabled");
216233
else
@@ -259,6 +276,7 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci)
259276

260277
switch (cpu_class) {
261278
case CPU_CLASS_ARMv7:
279+
case CPU_CLASS_PJ4B:
262280
break;
263281
default:
264282
if (cpu_classes[cpu_class].class_option != NULL)

‎sys/arch/arm/arm/cpufunc.c‎

Lines changed: 106 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -134,6 +134,62 @@ struct cpu_functions armv7_cpufuncs = {
134134
armv7_context_switch, /* context_switch */
135135
armv7_setup /* cpu setup */
136136
};
137+
138+
struct cpu_functions pj4bv7_cpufuncs = {
139+
/* CPU functions */
140+
141+
cpufunc_id, /* id */
142+
armv7_drain_writebuf, /* cpwait */
143+
144+
/* MMU functions */
145+
146+
cpufunc_control, /* control */
147+
cpufunc_domains, /* Domain */
148+
armv7_setttb, /* Setttb */
149+
cpufunc_dfsr, /* dfsr */
150+
cpufunc_dfar, /* dfar */
151+
cpufunc_ifsr, /* ifsr */
152+
cpufunc_ifar, /* ifar */
153+
154+
/* TLB functions */
155+
156+
armv7_tlb_flushID, /* tlb_flushID */
157+
armv7_tlb_flushID_SE, /* tlb_flushID_SE */
158+
armv7_tlb_flushI, /* tlb_flushI */
159+
armv7_tlb_flushI_SE, /* tlb_flushI_SE */
160+
armv7_tlb_flushD, /* tlb_flushD */
161+
armv7_tlb_flushD_SE, /* tlb_flushD_SE */
162+
163+
/* Cache operations */
164+
165+
armv7_icache_sync_all, /* icache_sync_all */
166+
armv7_icache_sync_range, /* icache_sync_range */
167+
168+
armv7_dcache_wbinv_all, /* dcache_wbinv_all */
169+
armv7_dcache_wbinv_range, /* dcache_wbinv_range */
170+
armv7_dcache_inv_range, /* dcache_inv_range */
171+
armv7_dcache_wb_range, /* dcache_wb_range */
172+
173+
armv7_idcache_wbinv_all, /* idcache_wbinv_all */
174+
armv7_idcache_wbinv_range, /* idcache_wbinv_range */
175+
176+
cpufunc_nullop, /* sdcache_wbinv_all */
177+
(void *)cpufunc_nullop, /* sdcache_wbinv_range */
178+
(void *)cpufunc_nullop, /* sdcache_inv_range */
179+
(void *)cpufunc_nullop, /* sdcache_wb_range */
180+
(void *)cpufunc_nullop, /* sdcache_drain_writebuf */
181+
182+
/* Other functions */
183+
184+
cpufunc_nullop, /* flush_prefetchbuf */
185+
armv7_drain_writebuf, /* drain_writebuf */
186+
187+
pj4b_cpu_sleep, /* sleep (wait for interrupt) */
188+
189+
/* Soft functions */
190+
armv7_context_switch, /* context_switch */
191+
pj4bv7_setup /* cpu setup */
192+
};
137193
#endif /* CPU_ARMv7 */
138194

139195
/*
@@ -323,6 +379,25 @@ set_cpufuncs()
323379
armv7_dcache_index_max = 0U - armv7_dcache_index_inc;
324380
pmap_pte_init_armv7();
325381

382+
/* Use powersave on this CPU. */
383+
cpu_do_powersave = 1;
384+
return 0;
385+
}
386+
if ((cputype == CPU_ID_MV88SV581X_V6 ||
387+
cputype == CPU_ID_MV88SV581X_V7 ||
388+
cputype == CPU_ID_MV88SV584X_V7 ||
389+
cputype == CPU_ID_ARM_88SV581X_V6 ||
390+
cputype == CPU_ID_ARM_88SV581X_V7)) {
391+
cpufuncs = pj4bv7_cpufuncs;
392+
arm_get_cachetype_cp15v7();
393+
armv7_dcache_sets_inc = 1U << arm_dcache_l2_linesize;
394+
armv7_dcache_sets_max =
395+
(1U << (arm_dcache_l2_linesize + arm_dcache_l2_nsets)) -
396+
armv7_dcache_sets_inc;
397+
armv7_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc);
398+
armv7_dcache_index_max = 0U - armv7_dcache_index_inc;
399+
pmap_pte_init_armv7();
400+
326401
/* Use powersave on this CPU. */
327402
cpu_do_powersave = 1;
328403
return 0;
@@ -398,4 +473,35 @@ armv7_setup()
398473
/* And again. */
399474
cpu_idcache_wbinv_all();
400475
}
476+
477+
void
478+
pj4bv7_setup()
479+
{
480+
int cpuctrl;
481+
482+
pj4b_config();
483+
484+
cpuctrl = CPU_CONTROL_MMU_ENABLE;
485+
//cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
486+
cpuctrl |= CPU_CONTROL_DC_ENABLE;
487+
cpuctrl |= CPU_CONTROL_IC_ENABLE;
488+
cpuctrl |= (0xf << 3);
489+
cpuctrl |= CPU_CONTROL_BPRD_ENABLE;
490+
cpuctrl |= (0x5 << 16) | (1 < 22);
491+
cpuctrl |= CPU_CONTROL_XP;
492+
493+
if (vector_page == ARM_VECTORS_HIGH)
494+
cpuctrl |= CPU_CONTROL_VECRELOC;
495+
496+
/* Clear out the cache */
497+
cpu_idcache_wbinv_all();
498+
499+
/* Set the control register */
500+
cpu_control(0xffffffff, cpuctrl);
501+
502+
/* And again. */
503+
cpu_idcache_wbinv_all();
504+
505+
curcpu()->ci_ctrl = cpuctrl;
506+
}
401507
#endif /* CPU_ARMv7 */

‎sys/arch/arm/arm/cpufunc_asm_pj4b.S‎

Lines changed: 86 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,86 @@
1+
/* $NetBSD: cpufunc_asm_pj4b.S,v 1.7 2015/04/15 10:52:18 hsuenaga Exp $ */
2+
3+
/*******************************************************************************
4+
Copyright (C) Marvell International Ltd. and its affiliates
5+
6+
Developed by Semihalf
7+
8+
********************************************************************************
9+
Marvell BSD License
10+
11+
If you received this File from Marvell, you may opt to use, redistribute and/or
12+
modify this File under the following licensing terms.
13+
Redistribution and use in source and binary forms, with or without modification,
14+
are permitted provided that the following conditions are met:
15+
16+
* Redistributions of source code must retain the above copyright notice,
17+
this list of conditions and the following disclaimer.
18+
19+
* Redistributions in binary form must reproduce the above copyright
20+
notice, this list of conditions and the following disclaimer in the
21+
documentation and/or other materials provided with the distribution.
22+
23+
* Neither the name of Marvell nor the names of its contributors may be
24+
used to endorse or promote products derived from this software without
25+
specific prior written permission.
26+
27+
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
28+
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
29+
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30+
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
31+
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32+
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33+
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
34+
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35+
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36+
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37+
38+
*******************************************************************************/
39+
40+
#include <arm/armreg.h>
41+
#include <machine/asm.h>
42+
43+
.Lpj4b_cache_line_size:
44+
.word _C_LABEL(arm_dcache_align)
45+
46+
ENTRY(pj4b_cpu_sleep)
47+
dsb
48+
wfi @ wait for an interrupt
49+
dsb @ Erratum#ARM-CPU-4742
50+
mov pc, lr
51+
52+
ENTRY(pj4b_config)
53+
/* Set Auxiliary Debug Modes Control 0 register */
54+
mrc p15, 1, r0, c15, c1, 0
55+
bic r0, r0, #(1 << 12) @ Erratum#ARM-CPU-6136
56+
@ LDSTM 1st issue is single word
57+
orr r0, r0, #(1 << 22) @ DVM_WAKEUP enable
58+
mcr p15, 1, r0, c15, c1, 0
59+
60+
/* Set Auxiliary Debug Modes Control 1 register */
61+
mrc p15, 1, r0, c15, c1, 1
62+
bic r0, r0, #(1 << 2) @ Erratum#ARM-CPU-6409
63+
@ Disable static branch prediction
64+
orr r0, r0, #(1 << 5) @ STREX backoff disable
65+
mcr p15, 1, r0, c15, c1, 1
66+
67+
/* Set Auxiliary Debug Modes Control 2 register */
68+
mrc p15, 1, r0, c15, c1, 2
69+
bic r0, r0, #(1 << 23) @ Enable fast LDR
70+
orr r0, r0, #(1 << 25) @ Intervention Interleave disable
71+
orr r0, r0, #(1 << 27) @ Critical word 1st sequencing dis.
72+
orr r0, r0, #(1 << 29) @ Disable MO device R/W
73+
orr r0, r0, #(1 << 30) @ L1 cache strict round-robin
74+
orr r0, r0, #(1 << 31) @ Enable write evict
75+
mcr p15, 1, r0, c15, c1, 2
76+
77+
/* Set Auxiliary FUnction Modes Control 0 register */
78+
mrc p15, 1, r0, c15, c2, 0
79+
#ifdef MULTIPROCESSOR
80+
orr r0, r0, #(1 << 1) @ SMP/nAMP enable
81+
#endif
82+
orr r0, r0, #(1 << 2) @ L2 parity enable
83+
orr r0, r0, #(1 << 8) @ Cache & TLB maintenance broadcast
84+
mcr p15, 1, r0, c15, c2, 0
85+
86+
mov pc, lr

‎sys/arch/arm/conf/files.arm‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,7 @@ file arch/arm/arm/copystr.S
4343
file arch/arm/arm/cpufunc.c
4444
file arch/arm/arm/cpufunc_asm.S
4545
file arch/arm/arm/cpufunc_asm_armv7.S cpu_armv7
46+
file arch/arm/arm/cpufunc_asm_pj4b.S cpu_armv7
4647
file arch/arm/arm/process_machdep.c
4748
file arch/arm/arm/sig_machdep.c
4849
file arch/arm/arm/sigcode.S

‎sys/arch/arm/include/armreg.h‎

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -164,7 +164,15 @@
164164
#define CPU_ID_CORTEX_A15_R3 0x413fc0f0
165165
#define CPU_ID_CORTEX_A15_R4 0x414fc0f0
166166
#define CPU_ID_CORTEX_A15_MASK 0xff0ffff0
167-
167+
#define CPU_ID_MV88SV58XX_P(n) ((n & 0xff0fff00) == 0x560f5800)
168+
#define CPU_ID_MV88SV581X_V6 0x560f5810 /* Marvell Sheeva 88SV581x v6 Core */
169+
#define CPU_ID_MV88SV581X_V7 0x561f5810 /* Marvell Sheeva 88SV581x v7 Core */
170+
#define CPU_ID_MV88SV584X_V6 0x561f5840 /* Marvell Sheeva 88SV584x v6 Core */
171+
#define CPU_ID_MV88SV584X_V7 0x562f5840 /* Marvell Sheeva 88SV584x v7 Core */
172+
/* Marvell's CPUIDs with ARM ID in implementor field */
173+
#define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */
174+
#define CPU_ID_ARM_88SV581X_V7 0x413fc080 /* Marvell Sheeva 88SV581x v7 Core */
175+
#define CPU_ID_ARM_88SV584X_V6 0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */
168176

169177
/* ARM3-specific coprocessor 15 registers */
170178
#define ARM3_CP15_FLUSH 1
@@ -235,6 +243,7 @@
235243
/* below were added by V6 */
236244
#define CPU_CONTROL_FI (1<<21) /* FI: fast interrupts */
237245
#define CPU_CONTROL_U (1<<22) /* U: Unaligned */
246+
#define CPU_CONTROL_XP (1<<23) /* XP: extended page table */
238247
#define CPU_CONTROL_VE (1<<24) /* VE: Vector enable */
239248
#define CPU_CONTROL_EE (1<<25) /* EE: Exception Endianness */
240249
#define CPU_CONTROL_L2 (1<<25) /* L2: L2 cache enable */

‎sys/arch/arm/include/cpufunc.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -245,6 +245,10 @@ void armv7_dcache_wb_range (vaddr_t, vsize_t);
245245
void armv7_idcache_wbinv_all (void);
246246
void armv7_idcache_wbinv_range (vaddr_t, vsize_t);
247247

248+
void pj4b_cpu_sleep (int mode);
249+
void pj4b_config (void);
250+
void pj4bv7_setup (void);
251+
248252
extern unsigned armv7_dcache_sets_max;
249253
extern unsigned armv7_dcache_sets_inc;
250254
extern unsigned armv7_dcache_index_max;

0 commit comments

Comments
 (0)