Speed up CI

[sequencer]

Contributor Checklist

• Did you add Scaladoc to every public function/method?
• Did you add at least one test demonstrating the PR?
• Did you delete any extraneous printlns/debugging code?
• Did you specify the type of improvement?
• Did you add appropriate documentation in docs/src?
• Did you state the API impact?
• Did you specify the code generation impact?
• Did you request a desired merge strategy?
• Did you add text to be included in the Release Notes for this change?

Type of Improvement

API Impact

Backend Code Generation Impact

Desired Merge Strategy

Release Notes

Reviewer Checklist (only modified by reviewer)

• Did you add the appropriate labels?
• Did you mark the proper milestone (3.2.x, 3.3.x, 3.4.x, 3.5.0) ?
• Did you review?
• Did you check whether all relevant Contributor checkboxes have been checked?
• Did you mark as Please Merge?

[sequencer]

Reopen #2036 due to CI issue.

[sequencer]

Test in Mac failed with verilator/verilator#3031
So just gave up Mac CI :(

[sequencer]

https://github.com/chipsalliance/chisel3/pull/2043/checks?check_run_id=3358132535#step:13:5720

WTF here?

[sequencer]

Wed, 18 Aug 2021 08:54:43 GMT
[info] ImplicitModule directly in a RawModule in an ImplicitModule
6626
Wed, 18 Aug 2021 08:54:43 GMT
Elaborating design...
6627
Wed, 18 Aug 2021 08:54:43 GMT
[info] - should fail
6628
Wed, 18 Aug 2021 09:40:57 GMT
[info] - Infering widths on huge Vecs should not cause a stack overflow
6629
Wed, 18 Aug 2021 09:40:57 GMT
Elaborating design...
6630
Wed, 18 Aug 2021 09:40:57 GMT
Done elaborating.

[jackkoenig]

Replaced by #2341