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1 file changed
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lines changedSubmodule circt-verilog updated 18 files
- frontends/PyCDE/src/pycde/bsp/common.py+66-3
- include/circt/Conversion/HWToSMT.h+2-1
- include/circt/Conversion/Passes.td+6
- include/circt/Dialect/Moore/MooreOps.td+17
- lib/Conversion/CombToSMT/CombToSMT.cpp+1-1
- lib/Conversion/HWToBTOR2/HWToBTOR2.cpp+54-8
- lib/Conversion/HWToSMT/HWToSMT.cpp+37-18
- lib/Conversion/ImportVerilog/Expressions.cpp+72-8
- lib/Conversion/ImportVerilog/ImportVerilogInternals.h+4-3
- lib/Conversion/ImportVerilog/Structure.cpp+90-26
- lib/Conversion/ImportVerilog/Types.cpp+2
- lib/Dialect/ESI/runtime/cpp/lib/Manifest.cpp+1-1
- test/Conversion/HWToBTOR2/comb.mlir+8-3
- test/Conversion/HWToBTOR2/errors.mlir+2-2
- test/Conversion/HWToSMT/hw-to-smt.mlir+21
- test/Conversion/ImportVerilog/basic.sv+34
- test/Conversion/ImportVerilog/builtins.sv+7
- test/Conversion/ImportVerilog/classes.sv+120
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