Version 1.3.31

Author: mikhailmoiseev

cmake/svc_target.cmake

@@ -14,13 +14,16 @@ function(svc_target exe_target)
     # PORT_MAP_GENERATE    -- generate port map file for SV/SC mixed simulation
     # NO_REMOVE_EXTRA_CODE -- disable removing unused variable and extra code
     # INIT_LOCAL_VARS      -- initialize local variables at declaration with zero
+    # INIT_RESET_LOCAL_VARS -- initialize CTHREAD reset section local variables 
+    #                          at declaration with zero
     # ELAB_ONLY  -- run elaboration without process generation
     # WILL_FAIL  -- test will fail on non-synthesizable code
     set(boolOptions REPLACE_CONST_VALUE 
                     NO_SVA_GENERATE
                     PORT_MAP_GENERATE
                     NO_REMOVE_EXTRA_CODE
                     INIT_LOCAL_VARS
+                    INIT_RESET_LOCAL_VARS
                     ELAB_ONLY 
                     WILL_FAIL)
 
@@ -59,6 +62,10 @@ function(svc_target exe_target)
         set(INIT_LOCAL_VARS -init_local_vars)
     endif()
 
+    if (${PARAM_INIT_RESET_LOCAL_VARS})
+        set(INIT_RESET_LOCAL_VARS -init_reset_local_vars)
+    endif()
+
     if (${PARAM_REPLACE_CONST_VALUE})
         set(REPLACE_CONST_VALUE -replace_const_value)
     endif()
@@ -157,6 +164,7 @@ function(svc_target exe_target)
             ${PORT_MAP_GENERATE}
             ${NO_REMOVE_EXTRA_CODE}
             ${INIT_LOCAL_VARS}
+            ${INIT_RESET_LOCAL_VARS}
             ${ELAB_ONLY}
             --
             -D__SC_TOOL__ -D__SC_TOOL_ANALYZE__ -DNDEBUG

doc/install.tex

@@ -198,7 +198,7 @@ \subsubsection{Generate SV code for all examples, tests and designs}
 For {\tt counter} example:
 % 
 \begin{lstlisting}[language=bash]
-$ cd examples/counter                # go to counter example folder 
+$ cd icsc/examples/counter           # go to counter example folder 
 $ cat sv_out/counter.sv              # see generated SystemVerilog file 
 \end{lstlisting}
 
@@ -207,10 +207,10 @@ \subsubsection{Run SystemC simulation}
 SystemC simulation for examples and tests can be run with:
 \begin{lstlisting}[language=bash]
 $ cd $ICSC_HOME
-$ mkdir build && cd build
+$ mkdir -p build && cd build
 $ cmake ../                          # prepare Makefiles 
 $ make counter                       # compile SystemC simulation for counter example
-$ cd examples/counter                # go to counter example folder
+$ cd icsc/examples/counter           # go to counter example folder
 $ ./counter                          # run SystemC simulation 
 \end{lstlisting}
 

doc/prepare.tex

@@ -303,6 +303,21 @@ \subsection{Clock and reset}
 
 Clocked thread process ({\tt SC\_CTHREAD} and {\tt SC\_THREAD}) is activated by one clock edge. Method process ({\tt SC\_METHOD}) can be sensitive to any change in the signals including clock positive or/and negative edge.
 
+Method process can have arbitrary number of resets in its sensitivity list. 
+\begin{lstlisting}[style=mycpp]
+SC_CTOR(test_reset) {
+   SC_METHOD(proc);
+   sensitive << sreset << areset << ...;       
+}
+void proc() {
+   if (!sreset || !areset) {
+       // Reset behavior
+   } else {
+       // Normal behavior
+   }
+}
+\end{lstlisting}
+
 Clocked thread process can have one, several or no reset. Clocked thread cannot have more than one asynchronous reset, but can have multiple synchronous resets. SystemC synthesizable subset does not allow clocked thread without resets and multiple synchronous resets. As soon as no reset clocked threads and clocked thread with multiple synchronous resets are required for some applications that is supported by ICSC tool. 
 
 Method process can be sensitive to all resets required.
@@ -354,7 +369,9 @@ \subsection{Clock and reset}
 }
 \end{lstlisting}
 
-For thread process ICSC generates pair of {\tt always\_comb} and {\tt always\_ff} blocks as described in~\ref{section:noreset}.
+For clocked thread process ICSC generates pair of {\tt always\_comb} and {\tt always\_ff} blocks as described in~\ref{section:thread_gen}.
+
+There are some limitation to variable use in reset section of clocked thread described in~\ref{section:reg_in_reset}.
 
 \subsection{Data types}
 

doc/trans_flow.tex

@@ -74,7 +74,7 @@ \subsection{Module generation}\label{section:module_gen}
 localparam logic signed [31:0] D = 'd42;
 
 //------------------------------------------------------------------------------
-// Assignments generated for SystemC array of channels
+// Assignments generated for SystemC channel arrays
 assign f[0] = f0;
 assign f[1] = f1;
 
@@ -388,6 +388,51 @@ \subsection{Thread process generation}\label{section:thread_gen}
 end
 \end{lstlisting}
 
+\subsection{Register variables in thread reset section}\label{section:reg_in_reset}
+
+There are some limitations to use register variables in reset section of clocked thread. Register variable is a variable which keeps its values between thread states. Register variable {\tt i} is represented with a pair of variables {\tt i} and {\tt i\_next} in SV code. Register next to current value has non-blocking assignment in {\tt always\_ff} block, therefore such variable cannot have blocking assignment in reset section. For operations which modify register variable in reset section error is reported:
+%
+\begin{lstlisting}[style=mycpp]
+void proc() {
+    int i = 1;      // Register variable
+    i++;            // Error reported
+    i += 1;         // Error reported
+    wait();
+    while (true) {
+       out = i;     // Value from reset used here
+       wait();
+    }        
+\end{lstlisting}
+
+\begin{lstlisting}[style=myverilog]
+logic signed [31:0] i;
+logic signed [31:0] i_next;
+always_ff @(posedge clk or negedge arstn) 
+begin : read_modify_reg_in_reset_ff
+    if ( ~arstn ) begin
+        i <= 1;
+        i++;         // Blocking assignment
+        i = i + 2;   
+    end
+    else begin
+        i <= i_next;
+    end
+\end{lstlisting}
+
+Another problem with register variable is reading it in reset section. As soon as the variables has non-blocking assignment it values could be incorrect in RHS of the following statements. For operations which read register variable in reset section warning is reported:
+%
+\begin{lstlisting}[style=mycpp]
+void proc() {
+    int i = 1;      // Register variable
+    int j = i;      // Warning reported
+    i = j;          // X results in SV simulation
+    wait();
+    while (true) {
+       out = i;     // Value from reset used here
+       wait();
+    }        
+\end{lstlisting}
+
 \subsection{Thread process without reset}\label{section:noreset}
 
 Thread process without reset supported with limitations: such process can have only one {\tt wait()} and cannot have any code in reset section.

doc/ug.pdf

@@ -12,25 +12,53 @@
 // and all DUT ports are bound.
 struct Tb : sc_module 
 {
-    sc_clock                clk{"clk", sc_time(1, SC_NS)};
+    sc_in_clk               clk{"clk"};
     sc_signal<bool>         rstn{"rstn"};
     sc_signal<sc_uint<4> >  counter{"counter"};
     sc_signal<bool>         even{"even"};
 
     Dut dut_inst{"dut_inst"};
-
+    
     SC_CTOR(Tb) 
     {
+        SC_CTHREAD(reset_test, clk.pos());
+        
         dut_inst.clk(clk);
         dut_inst.rstn(rstn);
         dut_inst.counter(counter);
         dut_inst.even(even);
+        
+        SC_METHOD(print_method);
+        sensitive << clk.pos();
+    }
+
+    void print_method() {
+        cout << sc_time_stamp() << "\t\t" << rstn.read() << "\t\t" 
+             << counter.read() << "\t\t" << even.read() << endl;
     }
+
+    void reset_test() {
+        rstn = 1;
+        wait(2);
+        
+        rstn = 0;
+        wait(3);
+        
+        rstn = 1;
+        wait(100);
+    }
+
 };
 
 int sc_main (int argc, char **argv) 
 {
+    sc_clock clk{"clk", sc_time(1, SC_NS)};
     Tb tb("tb");
-    sc_start();
+    tb.clk(clk);
+    
+    cout <<"Time\t\tReset\t\tCounter\t\tEven" << endl;
+    sc_start(20, SC_NS);
+    cout <<"\n\t\t*****Simulation complete*****" << endl;
+
     return 0;
 }

examples/counter/example.cpp

@@ -1,6 +1,6 @@
 //==============================================================================
 //
-// The code is generated by Intel Compiler for SystemC, version 1.3.20
+// The code is generated by Intel Compiler for SystemC, version 1.3.31
 // see more information at https://github.com/intel/systemc-compiler
 //
 //==============================================================================
@@ -174,39 +174,30 @@ logic almost_full_reg;
 
 always_comb 
 begin : asyncProc     // AdvFifo.h:176:5
-    if (1)
+    if (!out_valid_reg)
     begin
-        if (!out_valid_reg)
+        if (pop_enable_sig)
         begin
-            if (pop_enable_sig)
-            begin
-                data_out = data_in;
-                out_valid = push;
-                push_sig = push && !pop;
-            end else begin
-                out_valid = mcp_valid_reg;
-                data_out = mcp_data_reg;
-                push_sig = push;
-            end
+            data_out = data_in;
+            out_valid = push;
+            push_sig = push && !pop;
         end else begin
-            out_valid = 1;
-            data_out = pop_data;
+            out_valid = mcp_valid_reg;
+            data_out = mcp_data_reg;
             push_sig = push;
         end
+    end else begin
+        out_valid = 1;
+        data_out = pop_data;
+        push_sig = push;
     end
-    if (1)
+    if (push_enable_sig)
     begin
-        if (push_enable_sig)
-        begin
-            ready_to_push = pop && pop_enable && out_valid_reg || ready_push_reg;
-        end else begin
-            ready_to_push = ready_push_reg;
-        end
-    end
-    if (1)
-    begin
-        almost_full = almost_full_reg || (push && !pop && element_num == 6 - 3 - 1);
+        ready_to_push = pop && pop_enable && out_valid_reg || ready_push_reg;
+    end else begin
+        ready_to_push = ready_push_reg;
     end
+    almost_full = almost_full_reg || (push && !pop && element_num == 6 - 3 - 1);
 end
 
 //------------------------------------------------------------------------------
@@ -258,30 +249,24 @@ function void syncProc_func;
     ready_push_reg_next = ready_to_push;
     if (pop && pop_enable && out_valid_reg)
     begin
-        if (1)
+        if (popIndx_next == 6 - 1)
         begin
-            if (popIndx_next == 6 - 1)
-            begin
-                popIndx_next = 0;
-            end else begin
-                popIndx_next = popIndx_next + 1;
-            end
-            elementNum_next = elementNum_next - 1;
+            popIndx_next = 0;
+        end else begin
+            popIndx_next = popIndx_next + 1;
         end
+        elementNum_next = elementNum_next - 1;
     end
     if (push_sig && ready_to_push)
     begin
         fifo_buffer_flat_next[pushIndx_next] = data_in;
-        if (1)
+        if (pushIndx_next == 6 - 1)
         begin
-            if (pushIndx_next == 6 - 1)
-            begin
-                pushIndx_next = 0;
-            end else begin
-                pushIndx_next = pushIndx_next + 1;
-            end
-            elementNum_next = elementNum_next + 1;
+            pushIndx_next = 0;
+        end else begin
+            pushIndx_next = pushIndx_next + 1;
         end
+        elementNum_next = elementNum_next + 1;
     end
     pop_data_next = fifo_buffer_flat_next[popIndx_next];
     if (push_enable)
@@ -291,10 +276,7 @@ function void syncProc_func;
     end
     if (pop_enable)
     begin
-        if (1)
-        begin
-            element_num_next = elementNum_next;
-        end
+        element_num_next = elementNum_next;
         out_valid_reg_next = elementNum_next != 0;
     end
     element_num_d_next = element_num;
@@ -318,12 +300,9 @@ begin : syncProc_ff
         pushIndx <= 0;
         pop_data <= 0;
         fifo_buffer_flat[0] <= 32'd0;
-        if (1)
+        for (integer i = 1; i < 6; i++)
         begin
-            for (integer i = 1; i < 6; i++)
-            begin
-                fifo_buffer_flat[i] <= 32'd0;
-            end
+            fifo_buffer_flat[i] <= 32'd0;
         end
     end
     else begin

examples/dvcon20/dvcon_fifo.sv

@@ -112,8 +112,8 @@ Object* getOuterArray(SCDesign& designDB, Object* memberObj)
     return arrayObj;
 }
 
-const std::string SCElabASTConsumer::TOOL_VERSION = "1.3.26";
-const std::string SCElabASTConsumer::TOOL_DATE = "08 Jun,2021";
+const std::string SCElabASTConsumer::TOOL_VERSION = "1.3.31";
+const std::string SCElabASTConsumer::TOOL_DATE = "02 Jul,2021";
 
 void SCElabASTConsumer::HandleTranslationUnit(clang::ASTContext &astCtx)
 {
@@ -141,9 +141,9 @@ void SCElabASTConsumer::HandleTranslationUnit(clang::ASTContext &astCtx)
     //const char* optNames[] = {doModuleBuilder, doGenStmt};
     //const char* optNames[] = {doGenTerm, doGenCfg, doGenStmt, doModuleBuilder};
     //const char* optNames[] = {doConstCfg, doConstLoop, doConstStmt, doConstBlock, doModuleBuilder};
-    const char* optNames[] = {doModuleBuilder}; 
+    const char* optNames[] = {doGenStmt, doModuleBuilder}; 
     size_t optSize = sizeof(optNames)/sizeof(const char*);
-    //DebugOptions::enable(optNames, optSize);
+    //DebugOptions::enable(optNames, optSize); 
 
     //keepConstVariables = true;
 

sc_tool/lib/sc_tool/SCToolFrontendAction.cpp

@@ -44,6 +44,12 @@ cl::opt<bool> initLocalVars(
     cl::cat(ScToolCategory)
 );
 
+cl::opt<bool> initResetLocalVars(
+    "init_reset_local_vars",
+    cl::desc("Initialize CTHREAD reset local variables at declaration with zero"),
+    cl::cat(ScToolCategory)
+);
+
 cl::opt<bool> replaceConstByValue(
     "replace_const_value",
     cl::desc("Replace constant with its number value if possible"),

sc_tool/lib/sc_tool/ScCommandLine.cpp

@@ -22,6 +22,7 @@ extern llvm::cl::opt<bool>          noSvaGenerate;
 extern llvm::cl::opt<bool>          portMapGenerate;
 extern llvm::cl::opt<bool>          noRemoveExtraCode;
 extern llvm::cl::opt<bool>          initLocalVars;
+extern llvm::cl::opt<bool>          initResetLocalVars;
 extern llvm::cl::opt<bool>          replaceConstByValue;
 extern llvm::cl::opt<std::string>   modulePrefix;