Version 1.4.18 String initialization for SC integer supported

Author: mikhailmoiseev

doc/extensions.tex

@@ -1,8 +1,3 @@
-\section{Extensions}\label{section:extensions}
-
-\ifdefined\INTEL
-\include{extensions_intel} 
-\fi
 
 \subsection{Advanced FIFO}\label{section:adv_fifo}
 
@@ -126,13 +121,13 @@ \subsection{SystemVerilog intrinsic insertion}\label{section:black_box}
 
 \subsection{Memory module name}
 
-This section describes how to create own memory module with module name specified. 
+This section describes how to create a custom memory module with module name specified. 
 
-To support vendor memory it needs to specify memory module name at instantiation point and exclude the SV module code generation (memory module is external one). To exclude SV module code generation empty {\tt \_\_SC\_TOOL\_VERILOG\_MOD\_\_} should be used. To specify memory module name it needs to define {\tt \_\_SC\_TOOL\_MEMORY\_NAME\_\_} variable in the module body and initialize it with required name string.
+To support vendor memory it needs to specify memory module name at instantiation point and exclude the SV module code generation (memory module is external one). To exclude SV module code generation empty {\tt \_\_SC\_TOOL\_VERILOG\_MOD\_\_} should be used. To specify memory module name it needs to define {\tt \_\_SC\_TOOL\_MODULE\_NAME\_\_} variable in the module body and initialize it with required name string.
 
 If there are two instances of the same SystemC module, it is possible to give them different names, but {\tt \_\_SC\_TOOL\_VERILOG\_MOD\_\_} must be declared in the module. If {\tt \_\_SC\_TOOL\_VERILOG\_MOD\_\_} is not declared the SystemC module, only one SV module with first given name will be generated . 
 
-Module name could be specified for module with non-empty {\tt \_\_SC\_TOOL\_VERILOG\_MOD\_\_}, but module names in {\tt \_\_SC\_TOOL\_MEMORY\_NAME\_\_} and {\tt \_\_SC\_TOOL\_VERILOG\_MOD\_\_} should be the same.
+Module name could be specified for module with non-empty {\tt \_\_SC\_TOOL\_VERILOG\_MOD\_\_}, but module names in {\tt \_\_SC\_TOOL\_MODULE\_NAME\_\_} and {\tt \_\_SC\_TOOL\_VERILOG\_MOD\_\_} should be the same.
 
 If specified module name in module without {\tt \_\_SC\_TOOL\_VERILOG\_MOD\_\_} declaration conflicts with another module name, it updated with numeric suffix. Specified name in module with {\tt \_\_SC\_TOOL\_VERILOG\_MOD\_\_}  declaration never changed, so name uniqueness should be checked by user.
 
@@ -142,10 +137,10 @@ \subsection{Memory module name}
     // Disable Verilog module generation
     std::string __SC_TOOL_VERILOG_MOD__[] = "";  
     // Specify module name at instantiation
-    std::string __SC_TOOL_MEMORY_NAME__;             
+    std::string __SC_TOOL_MODULE_NAME__;             
     explicit memory_stub(const sc_module_name& name,
                          const char* verilogName = "") :
-        __SC_TOOL_MEMORY_NAME__(verilogName)
+        __SC_TOOL_MODULE_NAME__(verilogName)
     {}
 };
 

doc/install.tex

@@ -246,24 +246,3 @@ \subsection{Run tool for custom design}
 svc_target(mydesign ELAB_TOP tb.dut_inst)
 \end{lstlisting}
 
-
-\subsection{Tool options and defines}\label{section:tool_options}
-
-To run ICSC tool for the custom project it needs to create CMakeList.txt file. SystemVeriog code generation is done with {\tt svc\_target} function. {\tt svc\_target} is CMake function defined in {\tt \$ICSC\_HOME/lib64/cmake/SVC/svc\_target.cmake}.
-
-ICSC has several options, which can be specified as {\tt svc\_target} parameters:
-
-\begin{itemize}
-\item {\tt ELAB\_TOP} – design top module name, it needs to be specified if top module is instantiated outside of {\tt sc\_main()} or if there are more than one modules in {\tt sc\_main()};
-\item {\tt MODULE\_PREFIX} – module prefix string, no prefix if not specified, prefix applied for every module excluding Verilog intrinsic (module with {\tt \_\_SC\_TOOL\_VERILOG\_MOD\_\_}) and memory modules (modules with {\tt \_\_SC\_TOOL\_MEMORY\_NAME\_\_});
-\item {\tt REPLACE\_CONST\_VALUE} – replace constant with its evaluated value if possible, by default constant variable is used;
-\item {\tt INIT\_LOCAL\_VARS} – initialize non-initialized process local variables with zero to avoid latches, that related to CPP data types only, SC data types always initialized with 0;
-\item {\tt NO\_SVA\_GENERATE} – do not generate SVA from immediate and temporal SystemC assertions, normally SVA are generated;
-\item {\tt NO\_REMOVE\_EXTRA\_CODE} – do not remove unused variable and unused code in generated SV, normally such code is removed to improve readability.
-\end{itemize}
-
-ICSC tool provides {\tt \_\_SC\_TOOL\_\_} define for input SystemC project translation. This define used in temporal assertions and other ICSC library modules to have different behavior for simulation and SV generation. {\tt \_\_SC\_TOOL\_\_} can also be used in project code to hide pieces of code which is not targeted for translation to SystemVerilog.
-
-To completely disable SystemC temporal assertion macro {\tt SCT\_ASSERT\_OFF} can be defined. That allows to hide all assertion specific code to meet SystemC synthesizable standard requirements. {\tt SCT\_ASSERT\_OFF} is required if the SystemC design is passed through a tool which includes its own (not patched) SystemC library.
-
-

doc/preamble.tex

@@ -41,6 +41,19 @@
 	breakatwhitespace=true
 }
 
+\lstdefinestyle{mytext}{
+	frame=tb,
+	language=text,
+	aboveskip=3mm,
+	belowskip=3mm,
+	showstringspaces=false,
+	columns=flexible,
+	basicstyle={\small\ttfamily},
+	numbers=none,
+	breaklines=true,
+	breakatwhitespace=true
+}
+
 \lstset{frame=tb,
 	language=C++,
 	aboveskip=3mm,

doc/prepare.tex

@@ -890,6 +890,6 @@ \subsection{Naming restrictions}
 Suffix {\tt \_next} is used for register variables, so it is not recommended to use such suffix for SystemC variables.
 
 ICSC tool provides {\tt \_\_SC\_TOOL\_\_} define for input SystemC project translation. 
-Module/interface field {\tt\_\_SC\_TOOL\_MEMORY\_NAME\_\_} is reserved for vendor memory name. 
+Module/interface field {\tt\_\_SC\_TOOL\_MODULE\_NAME\_\_} is reserved for vendor memory name. 
 Module/interface field {\tt \_\_SC\_TOOL\_VERILOG\_MOD\_\_} is reserved for disable module generation in SystemVerilog code. 
 

doc/tool_options.tex

@@ -0,0 +1,67 @@
+
+\subsection{Tool options and defines}\label{section:tool_options}
+
+ICSC has several options, which can be specified as {\tt svc\_target} parameters. These options given in Table~\ref{tab:tool_opts}.
+
+
+\begin{table}
+\begin{tabular}{|l|l|}
+\hline
+Tool option & Description \\
+\hline
+{\tt ELAB\_TOP} & Design top module name, it needs to be specified if \\
+                & top module is instantiated outside of {\tt sc\_main()} \\
+                & or if there are more than one modules in {\tt sc\_main()} \\
+{\tt MODULE\_PREFIX} &  Module prefix string, no prefix if not specified, prefix \\         
+                & applied for every module excluding SV intrinsic, \\
+                & see~\ref{section:black_box} \\
+{\tt UNSIGNED}  & Unsigned mode for designs with unsigned arithmetic only, \\
+                & see~\ref{section:unsigned_mode} \\
+{\tt INIT\_LOCAL\_VARS} & Initialize non-initialized process local variables \\
+                & with 0 to avoid latches, that related to CPP data \\
+                & types only, SC data types always initialized with 0 \\
+{\tt INIT\_RESET\_LOCAL\_VARS} & Initialize non-initialized clocked thread local \\
+                & variables declared in reset section with zero, \\
+                & that related to CPP data types only, \\
+                & SC data types always initialized with 0 \\
+{\tt PORT\_MAP\_GENERATE} & Generate port map file and top module wrapper with \\
+                & flatten port arrays, port map file used for SC/SV \\
+                & mixed language simulation, top module wrapper used for \\
+                & logic synthesis tools which do not support unpacked \\
+                & port array in top module interface \\
+{\tt NO\_SVA\_GENERATE} & Do not generate SVA from immediate and temporal \\ 
+                & SystemC assertions, SVA are generated by default \\
+{\tt NO\_REMOVE\_EXTRA\_CODE} & Do not remove unused variable and unused code, \\ 
+                & normally such code is removed to improve readability \\
+\hline
+\end{tabular}
+\caption{{\tt svc\_target} parameters}
+\label{tab:tool_opts}
+\end{table}
+
+ICSC tool provides {\tt \_\_SC\_TOOL\_\_} define for input SystemC project translation. This define used in temporal assertions and other ICSC library modules to have different behavior for simulation and SV generation. {\tt \_\_SC\_TOOL\_\_} can also be used in project code to hide pieces of code which is not targeted for translation to SystemVerilog.
+
+To completely disable SystemC temporal assertion macro {\tt SCT\_ASSERT\_OFF} can be defined. That allows to hide all assertion specific code to meet SystemC synthesizable standard requirements. {\tt SCT\_ASSERT\_OFF} is required if the SystemC design is passed through a tool which includes its own (not patched) SystemC library.
+
+\subsubsection{Unsigned mode}\label{section:unsigned_mode}
+
+Unsigned mode is intended for designs with unsigned arithmetic only. That means all variables and constants types are unsigned, all expressions are evaluated as non-negative.
+
+In this mode variables and constants types as well as expressions types are checked to be unsigned. C99 types {\tt uint8\_t} and {\tt uint16\_t} (declared in {\tt <cstdint>}) are not recommended to use in this mode as they leads to false warnings. 
+
+Literals could be signed and unsigned (with suffix {\tt U}) in all operations except shifts. In shift expressions both arguments, including literals, should be unsigned.
+
+\begin{lstlisting}[style=mycpp]
+int i;                    // Warning, signed type variable  
+unsigned u = 1;     
+unsigned long ul = 2
+sc_uint<12> x = 3;
+sc_int<12> y;             // Warning, signed type variable 
+sc_biguint<32> bx = 4;
+uint8_t z;                
+const unsigned N = 42;
+ul = u + 1; 
+ul = 1 << x;              // Warning, signed literal in shift 
+ul = 1U << x;           
+ul = x + z;               // False warning for uint8_t
+\end{lstlisting}

doc/trans_flow.tex

@@ -209,10 +209,41 @@ \subsection{Variables generation}\label{section:var_gen}
 end
 \end{lstlisting}
 
+\subsection{Non-modified member variables generation}\label{section:non_modif_var_gen}
+Module or modular interface member variables which are non-modified in any process, considered as initialized at elaboration phase. Because of dynamic elaborator used in the tool, it is not possible to detect if a variable is not initialized at elaboration phase. 
+
+For such member variables which are scalar (non-array) and non-record type, SV local parameters are generated. 
+No local parameters generated for array and record members, so these variables remain non-initialized. Such member variable should be initialized in reset section of a process where it is used.
+
+\begin{lstlisting}[style=mycpp]
+class MyModule : public sc_module {
+  	bool C = true;
+	int D;
+   	unsigned E;
+
+	CTOR (MyModule) {
+   		D = 42;
+	}
+	void setE(unsigned par) { E = par; }
+}
+...
+MyModule m{"m"};
+...
+m.setE(43);   // In parent module constructor
+\end{lstlisting}
+%
+\begin{lstlisting}[style=myverilog]
+// Generated SystemVerilog
+localparam logic C = 1;
+localparam logic signed [31:0] D = 42;
+localparam logic [31:0] E = 43;
+\end{lstlisting}
+
+Nothing is generated if the variable is not used in any process. If such variable is member of array of modular interfaces, it should be used in a process of each modular interface.
 
 \subsection{Constants generation}\label{section:const_gen}
 
-For constants and static constants SV local parameters are generated. There is {\tt KEEP\_CONST\_VARIABLES} option to replace the constants in the code with their values, see~\ref{section:tool_options}. Constant is replaced with its value if the value if there is no reference to the constant. If constant is replaced with its value or not used in the code, no SV local parameter is generated.
+For constants and static constants SV local parameters are generated.
 
 \begin{lstlisting}[style=mycpp]
 static const bool C = true;
@@ -226,6 +257,8 @@ \subsection{Constants generation}\label{section:const_gen}
 localparam logic signed [31:0] D = 'd42;
 \end{lstlisting}
 
+There is {\tt REPLACE\_CONST\_VARIABLES} option to replace the constants in the code with their values, see~\ref{section:tool_options}. A constant is replaced with its value if the value if there is no reference to the constant. If constant is replaced with its value or not used in the code, no SV local parameter is generated.
+
 \subsection{Method process generation}\label{section:method_gen}
 
 Method process is directly translated into {\tt always\_comb} block. All the local variables of the method are translated into local variables in the {\tt always\_comb} block. 

doc/ug.pdf

@@ -6,9 +6,12 @@
 \subtitle{version 1.4}
 
 \author{Mikhail Moiseev}
+\ifdefined\INTEL
+\else
 \affiliation[obeypunctuation=true]{
 	\institution{Intel Corporation}
 }
+\fi
 
 %\email{mikhail.moiseev at intel.com}
 
@@ -23,8 +26,6 @@
 
 \pagebreak
 
-%\newif\INTEL
- 
 \section{Preface}
 
 Intel\textregistered Compiler for SystemC* (ICSC) is open source tool distributed under \href{https://github.com/intel/systemc-compiler/blob/main/LICENSE.txt}{Apache License v2.0 with LLVM Exceptions}. The source codes are available at \href{https://github.com/intel/systemc-compiler}{github.com/intel/systemc-compiler}.
@@ -69,11 +70,18 @@ \section{Terminology and abbreviations}
 \else
 \include{install}
 \fi
+\include{tool_options}
 
 \include{prepare}
 
 \include{trans_flow}
 
+\section{Extensions}\label{section:extensions}
+
+\ifdefined\INTEL
+\include{extensions_intel} 
+\fi
+
 \include{extensions}
 
 \include{errors}

doc/ug.tex

@@ -112,8 +112,8 @@ Object* getOuterArray(SCDesign& designDB, Object* memberObj)
     return arrayObj;
 }
 
-const std::string SCElabASTConsumer::TOOL_VERSION = "1.4.15";
-const std::string SCElabASTConsumer::TOOL_DATE = "10 Mar,2022";
+const std::string SCElabASTConsumer::TOOL_VERSION = "1.4.18";
+const std::string SCElabASTConsumer::TOOL_DATE = "15 Apr,2022";
 
 void SCElabASTConsumer::HandleTranslationUnit(clang::ASTContext &astCtx)
 {
@@ -125,25 +125,21 @@ void SCElabASTConsumer::HandleTranslationUnit(clang::ASTContext &astCtx)
                   TOOL_VERSION << ", " << TOOL_DATE << endl;
     cout << "--------------------------------------------------------------" << endl;
 
-    //replaceConstByValue.setValue(true);
-    //cout << "replaceConstByValue " << replaceConstByValue << endl;
-    
     //const char* optNames[] = {doElab};
     //const char* optNames[] = {doConstCfg, doGenCfg};
     //const char* optNames[] = {doModuleBuilder, doGenCfg, doGenTerm, doGenRTL, doGenStmt, doGenBlock};
     //const char* optNames[] = {doModuleBuilder, doGenCfg, doGenStmt, doGenFuncCall, doVerWriter};
     //const char* optNames[] = {doModuleBuilder, doGenStmt, doGenName, doGenRTL}; 
     //const char* optNames[] = {doModuleBuilder, doConstCfg, doConstTerm, doConstBlock, doGenCfg};
-    //const char* optNames[] = {doConstStmt}; 
-    //const char* optNames[] = {doConstCfg, doElab};
     //const char* optNames[] = {doGenCfg, doGenLoop, doGenBlock, doModuleBuilder}; 
     //const char* optNames[] = {doModuleBuilder, doConstStmt, doConstCfg/*, doState*/};
     //const char* optNames[] = {doModuleBuilder, doGenStmt};
     //const char* optNames[] = {doGenTerm, doGenCfg, doGenStmt, doModuleBuilder};
     //const char* optNames[] = {doConstCfg, doConstLoop, doConstStmt, doConstBlock, doModuleBuilder};
     //const char* optNames[] = {doConstCfg, doConstStmt, doModuleBuilder}; 
     //const char* optNames[] = {doGenFuncCall, doGenStmt, doModuleBuilder};  
-    const char* optNames[] = {doModuleBuilder};  
+    //const char* optNames[] = {doConstStmt, doUseDef, doModuleBuilder};  
+    const char* optNames[] = {doUseDef, doConstStmt, doModuleBuilder};  
     size_t optSize = sizeof(optNames)/sizeof(const char*);
     //DebugOptions::enable(optNames, optSize); 
 

sc_tool/lib/sc_tool/SCToolFrontendAction.cpp

@@ -56,12 +56,6 @@ cl::opt<bool> initResetLocalVars(
     cl::cat(ScToolCategory)
 );
 
-cl::opt<bool> replaceConstByValue(
-    "replace_const_value",
-    cl::desc("Replace constant with its number value if possible"),
-    cl::cat(ScToolCategory)
-);
-
 cl::opt<std::string> modulePrefix (
     "module_prefix",
     cl::desc("Module prefix string"),