@@ -309,6 +309,70 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
309309 QMP_PHY_INIT_CFG (QPHY_V3_PCS_RXEQTRAINING_RUN_TIME , 0x13 ),
310310};
311311
312+ static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl [] = {
313+ QMP_PHY_INIT_CFG (QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN , 0x0b ),
314+ QMP_PHY_INIT_CFG (QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 , 0x0f ),
315+ QMP_PHY_INIT_CFG (QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 , 0x4e ),
316+ QMP_PHY_INIT_CFG (QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 , 0x18 ),
317+ QMP_PHY_INIT_CFG (QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 , 0x77 ),
318+ QMP_PHY_INIT_CFG (QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 , 0x80 ),
319+ QMP_PHY_INIT_CFG (QSERDES_V3_RX_SIGDET_CNTRL , 0x03 ),
320+ QMP_PHY_INIT_CFG (QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL , 0x16 ),
321+ QMP_PHY_INIT_CFG (QSERDES_V3_RX_RX_MODE_00 , 0x05 ),
322+ QMP_PHY_INIT_CFG (QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE , 0x75 ),
323+ };
324+
325+ static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl [] = {
326+ /* FLL settings */
327+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_CNTRL2 , 0x83 ),
328+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_CNT_VAL_L , 0x09 ),
329+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_CNT_VAL_H_TOL , 0xa2 ),
330+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_MAN_CODE , 0x40 ),
331+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_FLL_CNTRL1 , 0x02 ),
332+
333+ /* Lock Det settings */
334+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_LOCK_DETECT_CONFIG1 , 0xd1 ),
335+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_LOCK_DETECT_CONFIG2 , 0x1f ),
336+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_LOCK_DETECT_CONFIG3 , 0x47 ),
337+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_POWER_STATE_CONFIG2 , 0x1b ),
338+
339+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_RX_SIGDET_LVL , 0xcc ),
340+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXMGN_V0 , 0x9f ),
341+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXMGN_V1 , 0x9f ),
342+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXMGN_V2 , 0xb7 ),
343+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXMGN_V3 , 0x4e ),
344+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXMGN_V4 , 0x65 ),
345+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXMGN_LS , 0x6b ),
346+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M6DB_V0 , 0x15 ),
347+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 , 0x0d ),
348+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M6DB_V1 , 0x15 ),
349+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 , 0x0d ),
350+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M6DB_V2 , 0x15 ),
351+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 , 0x0d ),
352+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M6DB_V3 , 0x15 ),
353+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 , 0x1d ),
354+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M6DB_V4 , 0x15 ),
355+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 , 0x0d ),
356+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M6DB_LS , 0x15 ),
357+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS , 0x0d ),
358+
359+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_RATE_SLEW_CNTRL , 0x02 ),
360+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK , 0x04 ),
361+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_TSYNC_RSYNC_TIME , 0x44 ),
362+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK , 0x04 ),
363+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L , 0xe7 ),
364+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H , 0x03 ),
365+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L , 0x40 ),
366+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H , 0x00 ),
367+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME , 0x75 ),
368+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK , 0x86 ),
369+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_RXEQTRAINING_RUN_TIME , 0x13 ),
370+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL , 0x04 ),
371+
372+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_REFGEN_REQ_CONFIG1 , 0x21 ),
373+ QMP_PHY_INIT_CFG (QPHY_V3_PCS_REFGEN_REQ_CONFIG2 , 0x60 ),
374+ };
375+
312376static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl [] = {
313377 QMP_PHY_INIT_CFG (QSERDES_V4_COM_SSC_EN_CENTER , 0x01 ),
314378 QMP_PHY_INIT_CFG (QSERDES_V4_COM_SSC_PER1 , 0x31 ),
@@ -807,6 +871,8 @@ struct qmp_combo_offsets {
807871 u16 usb3_pcs ;
808872 u16 usb3_pcs_usb ;
809873 u16 dp_serdes ;
874+ u16 dp_txa ;
875+ u16 dp_txb ;
810876 u16 dp_dp_phy ;
811877};
812878
@@ -973,6 +1039,21 @@ static const char * const sc7180_usb3phy_reset_l[] = {
9731039 "phy" ,
9741040};
9751041
1042+ static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
1043+ .com = 0x0000 ,
1044+ .txa = 0x1200 ,
1045+ .rxa = 0x1400 ,
1046+ .txb = 0x1600 ,
1047+ .rxb = 0x1800 ,
1048+ .usb3_serdes = 0x1000 ,
1049+ .usb3_pcs_misc = 0x1a00 ,
1050+ .usb3_pcs = 0x1c00 ,
1051+ .dp_serdes = 0x2000 ,
1052+ .dp_txa = 0x2200 ,
1053+ .dp_txb = 0x2600 ,
1054+ .dp_dp_phy = 0x2a00 ,
1055+ };
1056+
9761057static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {
9771058 .com = 0x0000 ,
9781059 .txa = 0x0400 ,
@@ -1170,6 +1251,51 @@ static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = {
11701251 .regs = qmp_v4_usb3phy_regs_layout ,
11711252};
11721253
1254+ static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
1255+ .offsets = & qmp_combo_offsets_v3 ,
1256+
1257+ .serdes_tbl = qmp_v3_usb3_serdes_tbl ,
1258+ .serdes_tbl_num = ARRAY_SIZE (qmp_v3_usb3_serdes_tbl ),
1259+ .tx_tbl = qmp_v3_usb3_tx_tbl ,
1260+ .tx_tbl_num = ARRAY_SIZE (qmp_v3_usb3_tx_tbl ),
1261+ .rx_tbl = sm6350_usb3_rx_tbl ,
1262+ .rx_tbl_num = ARRAY_SIZE (sm6350_usb3_rx_tbl ),
1263+ .pcs_tbl = sm6350_usb3_pcs_tbl ,
1264+ .pcs_tbl_num = ARRAY_SIZE (sm6350_usb3_pcs_tbl ),
1265+
1266+ .dp_serdes_tbl = qmp_v3_dp_serdes_tbl ,
1267+ .dp_serdes_tbl_num = ARRAY_SIZE (qmp_v3_dp_serdes_tbl ),
1268+ .dp_tx_tbl = qmp_v3_dp_tx_tbl ,
1269+ .dp_tx_tbl_num = ARRAY_SIZE (qmp_v3_dp_tx_tbl ),
1270+
1271+ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr ,
1272+ .serdes_tbl_rbr_num = ARRAY_SIZE (qmp_v3_dp_serdes_tbl_rbr ),
1273+ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr ,
1274+ .serdes_tbl_hbr_num = ARRAY_SIZE (qmp_v3_dp_serdes_tbl_hbr ),
1275+ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2 ,
1276+ .serdes_tbl_hbr2_num = ARRAY_SIZE (qmp_v3_dp_serdes_tbl_hbr2 ),
1277+ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3 ,
1278+ .serdes_tbl_hbr3_num = ARRAY_SIZE (qmp_v3_dp_serdes_tbl_hbr3 ),
1279+
1280+ .swing_hbr_rbr = & qmp_dp_v3_voltage_swing_hbr_rbr ,
1281+ .pre_emphasis_hbr_rbr = & qmp_dp_v3_pre_emphasis_hbr_rbr ,
1282+ .swing_hbr3_hbr2 = & qmp_dp_v3_voltage_swing_hbr3_hbr2 ,
1283+ .pre_emphasis_hbr3_hbr2 = & qmp_dp_v3_pre_emphasis_hbr3_hbr2 ,
1284+
1285+ .dp_aux_init = qmp_v3_dp_aux_init ,
1286+ .configure_dp_tx = qmp_v3_configure_dp_tx ,
1287+ .configure_dp_phy = qmp_v3_configure_dp_phy ,
1288+ .calibrate_dp_phy = qmp_v3_calibrate_dp_phy ,
1289+
1290+ .clk_list = qmp_v4_phy_clk_l ,
1291+ .num_clks = ARRAY_SIZE (qmp_v4_phy_clk_l ),
1292+ .reset_list = msm8996_usb3phy_reset_l ,
1293+ .num_resets = ARRAY_SIZE (msm8996_usb3phy_reset_l ),
1294+ .vreg_list = qmp_phy_vreg_l ,
1295+ .num_vregs = ARRAY_SIZE (qmp_phy_vreg_l ),
1296+ .regs = qmp_v3_usb3phy_regs_layout ,
1297+ };
1298+
11731299static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = {
11741300 .serdes_tbl = sm8150_usb3_serdes_tbl ,
11751301 .serdes_tbl_num = ARRAY_SIZE (sm8150_usb3_serdes_tbl ),
@@ -2639,8 +2765,13 @@ static int qmp_combo_parse_dt(struct qmp_combo *qmp)
26392765 qmp -> pcs_usb = base + offs -> usb3_pcs_usb ;
26402766
26412767 qmp -> dp_serdes = base + offs -> dp_serdes ;
2642- qmp -> dp_tx = base + offs -> txa ;
2643- qmp -> dp_tx2 = base + offs -> txb ;
2768+ if (offs -> dp_txa ) {
2769+ qmp -> dp_tx = base + offs -> dp_txa ;
2770+ qmp -> dp_tx2 = base + offs -> dp_txb ;
2771+ } else {
2772+ qmp -> dp_tx = base + offs -> txa ;
2773+ qmp -> dp_tx2 = base + offs -> txb ;
2774+ }
26442775 qmp -> dp_dp_phy = base + offs -> dp_dp_phy ;
26452776
26462777 qmp -> pipe_clk = devm_clk_get (dev , "usb3_pipe" );
@@ -2787,6 +2918,10 @@ static const struct of_device_id qmp_combo_of_match_table[] = {
27872918 .compatible = "qcom,sdm845-qmp-usb3-dp-phy" ,
27882919 .data = & sdm845_usb3dpphy_cfg ,
27892920 },
2921+ {
2922+ .compatible = "qcom,sm6350-qmp-usb3-dp-phy" ,
2923+ .data = & sm6350_usb3dpphy_cfg ,
2924+ },
27902925 {
27912926 .compatible = "qcom,sm8250-qmp-usb3-dp-phy" ,
27922927 .data = & sm8250_usb3dpphy_cfg ,
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