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chelsiocudbgdavem330
chelsiocudbg
authored and
davem330
committed
cxgb4: collect on-chip memory information
Collect memory layout of various on-chip memory regions. Move code for collecting on-chip memory information to cudbg_lib.c and update cxgb4_debugfs.c to use the common function. Also include cudbg_entity.h before cudbg_lib.h to avoid adding cudbg entity structure forward declarations in cudbg_lib.h. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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7 files changed

+374
-241
lines changed

7 files changed

+374
-241
lines changed

‎drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h‎

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -87,6 +87,41 @@ struct cudbg_tp_la {
8787
u8 data[0];
8888
};
8989

90+
static const char * const cudbg_region[] = {
91+
"DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
92+
"Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
93+
"Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
94+
"TDDP region:", "TPT region:", "STAG region:", "RQ region:",
95+
"RQUDP region:", "PBL region:", "TXPBL region:",
96+
"DBVFIFO region:", "ULPRX state:", "ULPTX state:",
97+
"On-chip queues:"
98+
};
99+
100+
struct cudbg_mem_desc {
101+
u32 base;
102+
u32 limit;
103+
u32 idx;
104+
};
105+
106+
struct cudbg_meminfo {
107+
struct cudbg_mem_desc avail[4];
108+
struct cudbg_mem_desc mem[ARRAY_SIZE(cudbg_region) + 3];
109+
u32 avail_c;
110+
u32 mem_c;
111+
u32 up_ram_lo;
112+
u32 up_ram_hi;
113+
u32 up_extmem2_lo;
114+
u32 up_extmem2_hi;
115+
u32 rx_pages_data[3];
116+
u32 tx_pages_data[4];
117+
u32 p_structs;
118+
u32 reserved[12];
119+
u32 port_used[4];
120+
u32 port_alloc[4];
121+
u32 loopback_used[NCHAN];
122+
u32 loopback_alloc[NCHAN];
123+
};
124+
90125
struct cudbg_cim_pif_la {
91126
int size;
92127
u8 data[0];

‎drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,7 @@ enum cudbg_dbg_entity_type {
5656
CUDBG_SGE_INDIRECT = 37,
5757
CUDBG_ULPRX_LA = 41,
5858
CUDBG_TP_LA = 43,
59+
CUDBG_MEMINFO = 44,
5960
CUDBG_CIM_PIF_LA = 45,
6061
CUDBG_CLK = 46,
6162
CUDBG_CIM_OBQ_RXQ0 = 47,

‎drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c‎

Lines changed: 288 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,12 +15,14 @@
1515
*
1616
*/
1717

18+
#include <linux/sort.h>
19+
1820
#include "t4_regs.h"
1921
#include "cxgb4.h"
2022
#include "cudbg_if.h"
2123
#include "cudbg_lib_common.h"
22-
#include "cudbg_lib.h"
2324
#include "cudbg_entity.h"
25+
#include "cudbg_lib.h"
2426

2527
static void cudbg_write_and_release_buff(struct cudbg_buffer *pin_buff,
2628
struct cudbg_buffer *dbg_buff)
@@ -84,6 +86,266 @@ static int cudbg_read_vpd_reg(struct adapter *padap, u32 addr, u32 len,
8486
return 0;
8587
}
8688

89+
static int cudbg_mem_desc_cmp(const void *a, const void *b)
90+
{
91+
return ((const struct cudbg_mem_desc *)a)->base -
92+
((const struct cudbg_mem_desc *)b)->base;
93+
}
94+
95+
int cudbg_fill_meminfo(struct adapter *padap,
96+
struct cudbg_meminfo *meminfo_buff)
97+
{
98+
struct cudbg_mem_desc *md;
99+
u32 lo, hi, used, alloc;
100+
int n, i;
101+
102+
memset(meminfo_buff->avail, 0,
103+
ARRAY_SIZE(meminfo_buff->avail) *
104+
sizeof(struct cudbg_mem_desc));
105+
memset(meminfo_buff->mem, 0,
106+
(ARRAY_SIZE(cudbg_region) + 3) * sizeof(struct cudbg_mem_desc));
107+
md = meminfo_buff->mem;
108+
109+
for (i = 0; i < ARRAY_SIZE(meminfo_buff->mem); i++) {
110+
meminfo_buff->mem[i].limit = 0;
111+
meminfo_buff->mem[i].idx = i;
112+
}
113+
114+
/* Find and sort the populated memory ranges */
115+
i = 0;
116+
lo = t4_read_reg(padap, MA_TARGET_MEM_ENABLE_A);
117+
if (lo & EDRAM0_ENABLE_F) {
118+
hi = t4_read_reg(padap, MA_EDRAM0_BAR_A);
119+
meminfo_buff->avail[i].base =
120+
cudbg_mbytes_to_bytes(EDRAM0_BASE_G(hi));
121+
meminfo_buff->avail[i].limit =
122+
meminfo_buff->avail[i].base +
123+
cudbg_mbytes_to_bytes(EDRAM0_SIZE_G(hi));
124+
meminfo_buff->avail[i].idx = 0;
125+
i++;
126+
}
127+
128+
if (lo & EDRAM1_ENABLE_F) {
129+
hi = t4_read_reg(padap, MA_EDRAM1_BAR_A);
130+
meminfo_buff->avail[i].base =
131+
cudbg_mbytes_to_bytes(EDRAM1_BASE_G(hi));
132+
meminfo_buff->avail[i].limit =
133+
meminfo_buff->avail[i].base +
134+
cudbg_mbytes_to_bytes(EDRAM1_SIZE_G(hi));
135+
meminfo_buff->avail[i].idx = 1;
136+
i++;
137+
}
138+
139+
if (is_t5(padap->params.chip)) {
140+
if (lo & EXT_MEM0_ENABLE_F) {
141+
hi = t4_read_reg(padap, MA_EXT_MEMORY0_BAR_A);
142+
meminfo_buff->avail[i].base =
143+
cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi));
144+
meminfo_buff->avail[i].limit =
145+
meminfo_buff->avail[i].base +
146+
cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi));
147+
meminfo_buff->avail[i].idx = 3;
148+
i++;
149+
}
150+
151+
if (lo & EXT_MEM1_ENABLE_F) {
152+
hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
153+
meminfo_buff->avail[i].base =
154+
cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi));
155+
meminfo_buff->avail[i].limit =
156+
meminfo_buff->avail[i].base +
157+
cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi));
158+
meminfo_buff->avail[i].idx = 4;
159+
i++;
160+
}
161+
} else {
162+
if (lo & EXT_MEM_ENABLE_F) {
163+
hi = t4_read_reg(padap, MA_EXT_MEMORY_BAR_A);
164+
meminfo_buff->avail[i].base =
165+
cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi));
166+
meminfo_buff->avail[i].limit =
167+
meminfo_buff->avail[i].base +
168+
cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi));
169+
meminfo_buff->avail[i].idx = 2;
170+
i++;
171+
}
172+
}
173+
174+
if (!i) /* no memory available */
175+
return CUDBG_STATUS_ENTITY_NOT_FOUND;
176+
177+
meminfo_buff->avail_c = i;
178+
sort(meminfo_buff->avail, i, sizeof(struct cudbg_mem_desc),
179+
cudbg_mem_desc_cmp, NULL);
180+
(md++)->base = t4_read_reg(padap, SGE_DBQ_CTXT_BADDR_A);
181+
(md++)->base = t4_read_reg(padap, SGE_IMSG_CTXT_BADDR_A);
182+
(md++)->base = t4_read_reg(padap, SGE_FLM_CACHE_BADDR_A);
183+
(md++)->base = t4_read_reg(padap, TP_CMM_TCB_BASE_A);
184+
(md++)->base = t4_read_reg(padap, TP_CMM_MM_BASE_A);
185+
(md++)->base = t4_read_reg(padap, TP_CMM_TIMER_BASE_A);
186+
(md++)->base = t4_read_reg(padap, TP_CMM_MM_RX_FLST_BASE_A);
187+
(md++)->base = t4_read_reg(padap, TP_CMM_MM_TX_FLST_BASE_A);
188+
(md++)->base = t4_read_reg(padap, TP_CMM_MM_PS_FLST_BASE_A);
189+
190+
/* the next few have explicit upper bounds */
191+
md->base = t4_read_reg(padap, TP_PMM_TX_BASE_A);
192+
md->limit = md->base - 1 +
193+
t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A) *
194+
PMTXMAXPAGE_G(t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A));
195+
md++;
196+
197+
md->base = t4_read_reg(padap, TP_PMM_RX_BASE_A);
198+
md->limit = md->base - 1 +
199+
t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) *
200+
PMRXMAXPAGE_G(t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A));
201+
md++;
202+
203+
if (t4_read_reg(padap, LE_DB_CONFIG_A) & HASHEN_F) {
204+
if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T5) {
205+
hi = t4_read_reg(padap, LE_DB_TID_HASHBASE_A) / 4;
206+
md->base = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A);
207+
} else {
208+
hi = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A);
209+
md->base = t4_read_reg(padap,
210+
LE_DB_HASH_TBL_BASE_ADDR_A);
211+
}
212+
md->limit = 0;
213+
} else {
214+
md->base = 0;
215+
md->idx = ARRAY_SIZE(cudbg_region); /* hide it */
216+
}
217+
md++;
218+
219+
#define ulp_region(reg) do { \
220+
md->base = t4_read_reg(padap, ULP_ ## reg ## _LLIMIT_A);\
221+
(md++)->limit = t4_read_reg(padap, ULP_ ## reg ## _ULIMIT_A);\
222+
} while (0)
223+
224+
ulp_region(RX_ISCSI);
225+
ulp_region(RX_TDDP);
226+
ulp_region(TX_TPT);
227+
ulp_region(RX_STAG);
228+
ulp_region(RX_RQ);
229+
ulp_region(RX_RQUDP);
230+
ulp_region(RX_PBL);
231+
ulp_region(TX_PBL);
232+
#undef ulp_region
233+
md->base = 0;
234+
md->idx = ARRAY_SIZE(cudbg_region);
235+
if (!is_t4(padap->params.chip)) {
236+
u32 fifo_size = t4_read_reg(padap, SGE_DBVFIFO_SIZE_A);
237+
u32 sge_ctrl = t4_read_reg(padap, SGE_CONTROL2_A);
238+
u32 size = 0;
239+
240+
if (is_t5(padap->params.chip)) {
241+
if (sge_ctrl & VFIFO_ENABLE_F)
242+
size = DBVFIFO_SIZE_G(fifo_size);
243+
} else {
244+
size = T6_DBVFIFO_SIZE_G(fifo_size);
245+
}
246+
247+
if (size) {
248+
md->base = BASEADDR_G(t4_read_reg(padap,
249+
SGE_DBVFIFO_BADDR_A));
250+
md->limit = md->base + (size << 2) - 1;
251+
}
252+
}
253+
254+
md++;
255+
256+
md->base = t4_read_reg(padap, ULP_RX_CTX_BASE_A);
257+
md->limit = 0;
258+
md++;
259+
md->base = t4_read_reg(padap, ULP_TX_ERR_TABLE_BASE_A);
260+
md->limit = 0;
261+
md++;
262+
263+
md->base = padap->vres.ocq.start;
264+
if (padap->vres.ocq.size)
265+
md->limit = md->base + padap->vres.ocq.size - 1;
266+
else
267+
md->idx = ARRAY_SIZE(cudbg_region); /* hide it */
268+
md++;
269+
270+
/* add any address-space holes, there can be up to 3 */
271+
for (n = 0; n < i - 1; n++)
272+
if (meminfo_buff->avail[n].limit <
273+
meminfo_buff->avail[n + 1].base)
274+
(md++)->base = meminfo_buff->avail[n].limit;
275+
276+
if (meminfo_buff->avail[n].limit)
277+
(md++)->base = meminfo_buff->avail[n].limit;
278+
279+
n = md - meminfo_buff->mem;
280+
meminfo_buff->mem_c = n;
281+
282+
sort(meminfo_buff->mem, n, sizeof(struct cudbg_mem_desc),
283+
cudbg_mem_desc_cmp, NULL);
284+
285+
lo = t4_read_reg(padap, CIM_SDRAM_BASE_ADDR_A);
286+
hi = t4_read_reg(padap, CIM_SDRAM_ADDR_SIZE_A) + lo - 1;
287+
meminfo_buff->up_ram_lo = lo;
288+
meminfo_buff->up_ram_hi = hi;
289+
290+
lo = t4_read_reg(padap, CIM_EXTMEM2_BASE_ADDR_A);
291+
hi = t4_read_reg(padap, CIM_EXTMEM2_ADDR_SIZE_A) + lo - 1;
292+
meminfo_buff->up_extmem2_lo = lo;
293+
meminfo_buff->up_extmem2_hi = hi;
294+
295+
lo = t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A);
296+
meminfo_buff->rx_pages_data[0] = PMRXMAXPAGE_G(lo);
297+
meminfo_buff->rx_pages_data[1] =
298+
t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) >> 10;
299+
meminfo_buff->rx_pages_data[2] = (lo & PMRXNUMCHN_F) ? 2 : 1;
300+
301+
lo = t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A);
302+
hi = t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A);
303+
meminfo_buff->tx_pages_data[0] = PMTXMAXPAGE_G(lo);
304+
meminfo_buff->tx_pages_data[1] =
305+
hi >= (1 << 20) ? (hi >> 20) : (hi >> 10);
306+
meminfo_buff->tx_pages_data[2] =
307+
hi >= (1 << 20) ? 'M' : 'K';
308+
meminfo_buff->tx_pages_data[3] = 1 << PMTXNUMCHN_G(lo);
309+
310+
meminfo_buff->p_structs = t4_read_reg(padap, TP_CMM_MM_MAX_PSTRUCT_A);
311+
312+
for (i = 0; i < 4; i++) {
313+
if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
314+
lo = t4_read_reg(padap,
315+
MPS_RX_MAC_BG_PG_CNT0_A + i * 4);
316+
else
317+
lo = t4_read_reg(padap, MPS_RX_PG_RSV0_A + i * 4);
318+
if (is_t5(padap->params.chip)) {
319+
used = T5_USED_G(lo);
320+
alloc = T5_ALLOC_G(lo);
321+
} else {
322+
used = USED_G(lo);
323+
alloc = ALLOC_G(lo);
324+
}
325+
meminfo_buff->port_used[i] = used;
326+
meminfo_buff->port_alloc[i] = alloc;
327+
}
328+
329+
for (i = 0; i < padap->params.arch.nchan; i++) {
330+
if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
331+
lo = t4_read_reg(padap,
332+
MPS_RX_LPBK_BG_PG_CNT0_A + i * 4);
333+
else
334+
lo = t4_read_reg(padap, MPS_RX_PG_RSV4_A + i * 4);
335+
if (is_t5(padap->params.chip)) {
336+
used = T5_USED_G(lo);
337+
alloc = T5_ALLOC_G(lo);
338+
} else {
339+
used = USED_G(lo);
340+
alloc = ALLOC_G(lo);
341+
}
342+
meminfo_buff->loopback_used[i] = used;
343+
meminfo_buff->loopback_alloc[i] = alloc;
344+
}
345+
346+
return 0;
347+
}
348+
87349
int cudbg_collect_reg_dump(struct cudbg_init *pdbg_init,
88350
struct cudbg_buffer *dbg_buff,
89351
struct cudbg_error *cudbg_err)
@@ -843,6 +1105,31 @@ int cudbg_collect_tp_la(struct cudbg_init *pdbg_init,
8431105
return rc;
8441106
}
8451107

1108+
int cudbg_collect_meminfo(struct cudbg_init *pdbg_init,
1109+
struct cudbg_buffer *dbg_buff,
1110+
struct cudbg_error *cudbg_err)
1111+
{
1112+
struct adapter *padap = pdbg_init->adap;
1113+
struct cudbg_buffer temp_buff = { 0 };
1114+
struct cudbg_meminfo *meminfo_buff;
1115+
int rc;
1116+
1117+
rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_meminfo), &temp_buff);
1118+
if (rc)
1119+
return rc;
1120+
1121+
meminfo_buff = (struct cudbg_meminfo *)temp_buff.data;
1122+
rc = cudbg_fill_meminfo(padap, meminfo_buff);
1123+
if (rc) {
1124+
cudbg_err->sys_err = rc;
1125+
cudbg_put_buff(&temp_buff, dbg_buff);
1126+
return rc;
1127+
}
1128+
1129+
cudbg_write_and_release_buff(&temp_buff, dbg_buff);
1130+
return rc;
1131+
}
1132+
8461133
int cudbg_collect_cim_pif_la(struct cudbg_init *pdbg_init,
8471134
struct cudbg_buffer *dbg_buff,
8481135
struct cudbg_error *cudbg_err)

‎drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -102,6 +102,9 @@ int cudbg_collect_ulprx_la(struct cudbg_init *pdbg_init,
102102
int cudbg_collect_tp_la(struct cudbg_init *pdbg_init,
103103
struct cudbg_buffer *dbg_buff,
104104
struct cudbg_error *cudbg_err);
105+
int cudbg_collect_meminfo(struct cudbg_init *pdbg_init,
106+
struct cudbg_buffer *dbg_buff,
107+
struct cudbg_error *cudbg_err);
105108
int cudbg_collect_cim_pif_la(struct cudbg_init *pdbg_init,
106109
struct cudbg_buffer *dbg_buff,
107110
struct cudbg_error *cudbg_err);
@@ -163,7 +166,8 @@ void cudbg_align_debug_buffer(struct cudbg_buffer *dbg_buff,
163166
u32 cudbg_cim_obq_size(struct adapter *padap, int qid);
164167
int cudbg_dump_context_size(struct adapter *padap);
165168

166-
struct cudbg_tcam;
169+
int cudbg_fill_meminfo(struct adapter *padap,
170+
struct cudbg_meminfo *meminfo_buff);
167171
void cudbg_fill_le_tcam_info(struct adapter *padap,
168172
struct cudbg_tcam *tcam_region);
169173
#endif /* __CUDBG_LIB_H__ */

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