@@ -122,6 +122,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
122122 .tcl_ring_retry = true,
123123 .tx_ring_size = DP_TCL_DATA_RING_SIZE ,
124124 .smp2p_wow_exit = false,
125+ .support_dual_stations = false,
125126 },
126127 {
127128 .hw_rev = ATH11K_HW_IPQ6018_HW10 ,
@@ -205,6 +206,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
205206 .tx_ring_size = DP_TCL_DATA_RING_SIZE ,
206207 .smp2p_wow_exit = false,
207208 .support_fw_mac_sequence = false,
209+ .support_dual_stations = false,
208210 },
209211 {
210212 .name = "qca6390 hw2.0" ,
@@ -255,7 +257,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
255257 .coldboot_cal_ftm = false,
256258 .cbcal_restart_fw = false,
257259 .fw_mem_mode = 0 ,
258- .num_vdevs = 16 + 1 ,
260+ .num_vdevs = 2 + 1 ,
259261 .num_peers = 512 ,
260262 .supports_suspend = true,
261263 .hal_desc_sz = sizeof (struct hal_rx_desc_ipq8074 ),
@@ -290,6 +292,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
290292 .tx_ring_size = DP_TCL_DATA_RING_SIZE ,
291293 .smp2p_wow_exit = false,
292294 .support_fw_mac_sequence = true,
295+ .support_dual_stations = true,
293296 },
294297 {
295298 .name = "qcn9074 hw1.0" ,
@@ -372,6 +375,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
372375 .tx_ring_size = DP_TCL_DATA_RING_SIZE ,
373376 .smp2p_wow_exit = false,
374377 .support_fw_mac_sequence = false,
378+ .support_dual_stations = false,
375379 },
376380 {
377381 .name = "wcn6855 hw2.0" ,
@@ -422,7 +426,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
422426 .coldboot_cal_ftm = false,
423427 .cbcal_restart_fw = false,
424428 .fw_mem_mode = 0 ,
425- .num_vdevs = 16 + 1 ,
429+ .num_vdevs = 2 + 1 ,
426430 .num_peers = 512 ,
427431 .supports_suspend = true,
428432 .hal_desc_sz = sizeof (struct hal_rx_desc_wcn6855 ),
@@ -457,6 +461,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
457461 .tx_ring_size = DP_TCL_DATA_RING_SIZE ,
458462 .smp2p_wow_exit = false,
459463 .support_fw_mac_sequence = true,
464+ .support_dual_stations = true,
460465 },
461466 {
462467 .name = "wcn6855 hw2.1" ,
@@ -505,7 +510,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
505510 .coldboot_cal_ftm = false,
506511 .cbcal_restart_fw = false,
507512 .fw_mem_mode = 0 ,
508- .num_vdevs = 16 + 1 ,
513+ .num_vdevs = 2 + 1 ,
509514 .num_peers = 512 ,
510515 .supports_suspend = true,
511516 .hal_desc_sz = sizeof (struct hal_rx_desc_wcn6855 ),
@@ -540,6 +545,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
540545 .tx_ring_size = DP_TCL_DATA_RING_SIZE ,
541546 .smp2p_wow_exit = false,
542547 .support_fw_mac_sequence = true,
548+ .support_dual_stations = true,
543549 },
544550 {
545551 .name = "wcn6750 hw1.0" ,
@@ -621,6 +627,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
621627 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750 ,
622628 .smp2p_wow_exit = true,
623629 .support_fw_mac_sequence = true,
630+ .support_dual_stations = false,
624631 },
625632 {
626633 .hw_rev = ATH11K_HW_IPQ5018_HW10 ,
@@ -702,6 +709,93 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
702709 .tx_ring_size = DP_TCL_DATA_RING_SIZE ,
703710 .smp2p_wow_exit = false,
704711 .support_fw_mac_sequence = false,
712+ .support_dual_stations = false,
713+ },
714+ {
715+ .name = "qca2066 hw2.1" ,
716+ .hw_rev = ATH11K_HW_QCA2066_HW21 ,
717+ .fw = {
718+ .dir = "QCA2066/hw2.1" ,
719+ .board_size = 256 * 1024 ,
720+ .cal_offset = 128 * 1024 ,
721+ },
722+ .max_radios = 3 ,
723+ .bdf_addr = 0x4B0C0000 ,
724+ .hw_ops = & wcn6855_ops ,
725+ .ring_mask = & ath11k_hw_ring_mask_qca6390 ,
726+ .internal_sleep_clock = true,
727+ .regs = & wcn6855_regs ,
728+ .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390 ,
729+ .host_ce_config = ath11k_host_ce_config_qca6390 ,
730+ .ce_count = 9 ,
731+ .target_ce_config = ath11k_target_ce_config_wlan_qca6390 ,
732+ .target_ce_count = 9 ,
733+ .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390 ,
734+ .svc_to_ce_map_len = 14 ,
735+ .ce_ie_addr = & ath11k_ce_ie_addr_ipq8074 ,
736+ .single_pdev_only = true,
737+ .rxdma1_enable = false,
738+ .num_rxmda_per_pdev = 2 ,
739+ .rx_mac_buf_ring = true,
740+ .vdev_start_delay = true,
741+ .htt_peer_map_v2 = false,
742+
743+ .spectral = {
744+ .fft_sz = 0 ,
745+ .fft_pad_sz = 0 ,
746+ .summary_pad_sz = 0 ,
747+ .fft_hdr_len = 0 ,
748+ .max_fft_bins = 0 ,
749+ .fragment_160mhz = false,
750+ },
751+
752+ .interface_modes = BIT (NL80211_IFTYPE_STATION ) |
753+ BIT (NL80211_IFTYPE_AP ),
754+ .supports_monitor = false,
755+ .full_monitor_mode = false,
756+ .supports_shadow_regs = true,
757+ .idle_ps = true,
758+ .supports_sta_ps = true,
759+ .coldboot_cal_mm = false,
760+ .coldboot_cal_ftm = false,
761+ .cbcal_restart_fw = false,
762+ .fw_mem_mode = 0 ,
763+ .num_vdevs = 2 + 1 ,
764+ .num_peers = 512 ,
765+ .supports_suspend = true,
766+ .hal_desc_sz = sizeof (struct hal_rx_desc_wcn6855 ),
767+ .supports_regdb = true,
768+ .fix_l1ss = false,
769+ .credit_flow = true,
770+ .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390 ,
771+ .hal_params = & ath11k_hw_hal_params_qca6390 ,
772+ .supports_dynamic_smps_6ghz = false,
773+ .alloc_cacheable_memory = false,
774+ .supports_rssi_stats = true,
775+ .fw_wmi_diag_event = true,
776+ .current_cc_support = true,
777+ .dbr_debug_support = false,
778+ .global_reset = true,
779+ .bios_sar_capa = & ath11k_hw_sar_capa_wcn6855 ,
780+ .m3_fw_support = true,
781+ .fixed_bdf_addr = false,
782+ .fixed_mem_region = false,
783+ .static_window_map = false,
784+ .hybrid_bus_type = false,
785+ .fixed_fw_mem = false,
786+ .support_off_channel_tx = true,
787+ .supports_multi_bssid = true,
788+
789+ .sram_dump = {
790+ .start = 0x01400000 ,
791+ .end = 0x0177ffff ,
792+ },
793+
794+ .tcl_ring_retry = true,
795+ .tx_ring_size = DP_TCL_DATA_RING_SIZE ,
796+ .smp2p_wow_exit = false,
797+ .support_fw_mac_sequence = true,
798+ .support_dual_stations = true,
705799 },
706800};
707801
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