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phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk
In preparation for support for additional platforms, convert the phy register access clock to using the clk_bulk interfaces. Newer SoCs like Google Tensor gs101 require additional clocks for access to additional (different) register areas (PHY, PMA, PCS), and converting to clk_bulk simplifies addition of those extra clocks. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20240617-usb-phy-gs101-v3-4-b66de9ae7424@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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‎drivers/phy/samsung/phy-exynos5-usbdrd.c‎

Lines changed: 39 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -185,6 +185,8 @@ struct exynos5_usbdrd_phy_config {
185185
struct exynos5_usbdrd_phy_drvdata {
186186
const struct exynos5_usbdrd_phy_config *phy_cfg;
187187
const struct phy_ops *phy_ops;
188+
const char * const *clk_names;
189+
int n_clks;
188190
const char * const *core_clk_names;
189191
int n_core_clks;
190192
u32 pmu_offset_usbdrd0_phy;
@@ -196,7 +198,7 @@ struct exynos5_usbdrd_phy_drvdata {
196198
* struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
197199
* @dev: pointer to device instance of this platform device
198200
* @reg_phy: usb phy controller register memory base
199-
* @clk: phy clock for register access
201+
* @clks: clocks for register access
200202
* @core_clks: core clocks for phy (ref, pipe3, utmi+, ITP, etc. as required)
201203
* @drv_data: pointer to SoC level driver data structure
202204
* @phys: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
@@ -209,7 +211,7 @@ struct exynos5_usbdrd_phy_drvdata {
209211
struct exynos5_usbdrd_phy {
210212
struct device *dev;
211213
void __iomem *reg_phy;
212-
struct clk *clk;
214+
struct clk_bulk_data *clks;
213215
struct clk_bulk_data *core_clks;
214216
const struct exynos5_usbdrd_phy_drvdata *drv_data;
215217
struct phy_usb_instance {
@@ -402,7 +404,7 @@ static int exynos5_usbdrd_phy_init(struct phy *phy)
402404
struct phy_usb_instance *inst = phy_get_drvdata(phy);
403405
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
404406

405-
ret = clk_prepare_enable(phy_drd->clk);
407+
ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
406408
if (ret)
407409
return ret;
408410

@@ -452,7 +454,7 @@ static int exynos5_usbdrd_phy_init(struct phy *phy)
452454
reg &= ~PHYCLKRST_PORTRESET;
453455
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
454456

455-
clk_disable_unprepare(phy_drd->clk);
457+
clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
456458

457459
return 0;
458460
}
@@ -464,7 +466,7 @@ static int exynos5_usbdrd_phy_exit(struct phy *phy)
464466
struct phy_usb_instance *inst = phy_get_drvdata(phy);
465467
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
466468

467-
ret = clk_prepare_enable(phy_drd->clk);
469+
ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
468470
if (ret)
469471
return ret;
470472

@@ -486,7 +488,7 @@ static int exynos5_usbdrd_phy_exit(struct phy *phy)
486488
PHYTEST_POWERDOWN_HSP;
487489
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
488490

489-
clk_disable_unprepare(phy_drd->clk);
491+
clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
490492

491493
return 0;
492494
}
@@ -811,14 +813,14 @@ static int exynos850_usbdrd_phy_init(struct phy *phy)
811813
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
812814
int ret;
813815

814-
ret = clk_prepare_enable(phy_drd->clk);
816+
ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
815817
if (ret)
816818
return ret;
817819

818820
/* UTMI or PIPE3 specific init */
819821
inst->phy_cfg->phy_init(phy_drd);
820822

821-
clk_disable_unprepare(phy_drd->clk);
823+
clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
822824

823825
return 0;
824826
}
@@ -831,7 +833,7 @@ static int exynos850_usbdrd_phy_exit(struct phy *phy)
831833
u32 reg;
832834
int ret;
833835

834-
ret = clk_prepare_enable(phy_drd->clk);
836+
ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
835837
if (ret)
836838
return ret;
837839

@@ -854,7 +856,7 @@ static int exynos850_usbdrd_phy_exit(struct phy *phy)
854856
reg &= ~CLKRST_LINK_SW_RST;
855857
writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
856858

857-
clk_disable_unprepare(phy_drd->clk);
859+
clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
858860

859861
return 0;
860862
}
@@ -873,11 +875,19 @@ static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd)
873875
struct clk *ref_clk;
874876
unsigned long ref_rate;
875877

876-
phy_drd->clk = devm_clk_get(phy_drd->dev, "phy");
877-
if (IS_ERR(phy_drd->clk)) {
878-
dev_err(phy_drd->dev, "Failed to get phy clock\n");
879-
return PTR_ERR(phy_drd->clk);
880-
}
878+
phy_drd->clks = devm_kcalloc(phy_drd->dev, phy_drd->drv_data->n_clks,
879+
sizeof(*phy_drd->clks), GFP_KERNEL);
880+
if (!phy_drd->clks)
881+
return -ENOMEM;
882+
883+
for (int i = 0; i < phy_drd->drv_data->n_clks; ++i)
884+
phy_drd->clks[i].id = phy_drd->drv_data->clk_names[i];
885+
886+
ret = devm_clk_bulk_get(phy_drd->dev, phy_drd->drv_data->n_clks,
887+
phy_drd->clks);
888+
if (ret)
889+
return dev_err_probe(phy_drd->dev, ret,
890+
"failed to get phy clock(s)\n");
881891

882892
phy_drd->core_clks = devm_kcalloc(phy_drd->dev,
883893
phy_drd->drv_data->n_core_clks,
@@ -939,6 +949,10 @@ static const struct exynos5_usbdrd_phy_config phy_cfg_exynos850[] = {
939949
},
940950
};
941951

952+
static const char * const exynos5_clk_names[] = {
953+
"phy",
954+
};
955+
942956
static const char * const exynos5_core_clk_names[] = {
943957
"ref",
944958
};
@@ -952,6 +966,8 @@ static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
952966
.phy_ops = &exynos5_usbdrd_phy_ops,
953967
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
954968
.pmu_offset_usbdrd1_phy = EXYNOS5420_USBDRD1_PHY_CONTROL,
969+
.clk_names = exynos5_clk_names,
970+
.n_clks = ARRAY_SIZE(exynos5_clk_names),
955971
.core_clk_names = exynos5_core_clk_names,
956972
.n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
957973
};
@@ -960,6 +976,8 @@ static const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = {
960976
.phy_cfg = phy_cfg_exynos5,
961977
.phy_ops = &exynos5_usbdrd_phy_ops,
962978
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
979+
.clk_names = exynos5_clk_names,
980+
.n_clks = ARRAY_SIZE(exynos5_clk_names),
963981
.core_clk_names = exynos5_core_clk_names,
964982
.n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
965983
};
@@ -969,6 +987,8 @@ static const struct exynos5_usbdrd_phy_drvdata exynos5433_usbdrd_phy = {
969987
.phy_ops = &exynos5_usbdrd_phy_ops,
970988
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
971989
.pmu_offset_usbdrd1_phy = EXYNOS5433_USBHOST30_PHY_CONTROL,
990+
.clk_names = exynos5_clk_names,
991+
.n_clks = ARRAY_SIZE(exynos5_clk_names),
972992
.core_clk_names = exynos5433_core_clk_names,
973993
.n_core_clks = ARRAY_SIZE(exynos5433_core_clk_names),
974994
};
@@ -977,6 +997,8 @@ static const struct exynos5_usbdrd_phy_drvdata exynos7_usbdrd_phy = {
977997
.phy_cfg = phy_cfg_exynos5,
978998
.phy_ops = &exynos5_usbdrd_phy_ops,
979999
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
1000+
.clk_names = exynos5_clk_names,
1001+
.n_clks = ARRAY_SIZE(exynos5_clk_names),
9801002
.core_clk_names = exynos5433_core_clk_names,
9811003
.n_core_clks = ARRAY_SIZE(exynos5433_core_clk_names),
9821004
};
@@ -985,6 +1007,8 @@ static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = {
9851007
.phy_cfg = phy_cfg_exynos850,
9861008
.phy_ops = &exynos850_usbdrd_phy_ops,
9871009
.pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
1010+
.clk_names = exynos5_clk_names,
1011+
.n_clks = ARRAY_SIZE(exynos5_clk_names),
9881012
.core_clk_names = exynos5_core_clk_names,
9891013
.n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
9901014
};

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