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Merge: Backport register read/write tracing support
MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-9/-/merge_requests/2490 Bugzilla: https://bugzilla.redhat.com/2196244 Backport register read/write tracing support. This allows debugging MMIO register accesses more conveniently. https://lore.kernel.org/all/cover.1652891705.git.quic_saipraka@quicinc.com/ https://lore.kernel.org/all/20221017143450.9161-1-quic_saipraka@quicinc.com/ # How to test - Apply this MR on top of main-automotive - Apply https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-9/-/merge_requests/2496 as well (kernel config) - Build and flash the kernel on a Qdrive3 - Execute: ``` echo 1 > /sys/kernel/tracing/events/rwmmio/enable cat /sys/kernel/tracing/trace ``` You should see a trace of register read/write events with a format similar to: ``` <idle>-0 [004] d...2.. 234.967386: rwmmio_post_read: clockevents_program_event+0xa8/0x120 -> arch_timer_set_next_event_virt_mem+0x150/0x2f4 width=32 val=0x1405fe20 addr=0xffff800008015008 <idle>-0 [004] d...2.. 234.967386: rwmmio_read: clockevents_program_event+0xa8/0x120 -> arch_timer_set_next_event_virt_mem+0x17c/0x2f4 width=32 addr=0xffff80000801500c <idle>-0 [004] d...2.. 234.967386: rwmmio_post_read: clockevents_program_event+0xa8/0x120 -> arch_timer_set_next_event_virt_mem+0x1ac/0x2f4 width=32 val=0x1 addr=0xffff80000801500c <idle>-0 [004] d...2.. 234.967386: rwmmio_write: clockevents_program_event+0xa8/0x120 -> arch_timer_set_next_event_virt_mem+0x1f4/0x2f4 width=64 val=0x11408e946 addr=0xffff800008015030 <idle>-0 [004] d...2.. 234.967387: rwmmio_post_write: clockevents_program_event+0xa8/0x120 -> arch_timer_set_next_event_virt_mem+0x228/0x2f4 width=64 val=0x11408e946 addr=0xffff800008015030 <idle>-0 [004] d...2.. 234.967387: rwmmio_write: clockevents_program_event+0xa8/0x120 -> arch_timer_set_next_event_virt_mem+0x258/0x2f4 width=32 val=0x1 addr=0xffff80000801503c <idle>-0 [004] d...2.. 234.967387: rwmmio_post_write: clockevents_program_event+0xa8/0x120 -> arch_timer_set_next_event_virt_mem+0x294/0x2f4 width=32 val=0x1 addr=0xffff80000801503c <idle>-0 [004] d...3.. 234.967389: rwmmio_read: gic_set_affinity+0x88/0x250 -> gic_peek_irq+0x80/0x140 width=32 addr=0xffff800008040104 <idle>-0 [004] d...3.. 234.967390: rwmmio_post_read: gic_set_affinity+0x88/0x250 -> gic_peek_irq+0xac/0x140 width=32 val=0x61 addr=0xffff800008040104 ``` Signed-off-by: Adrien Thierry <athierry@redhat.com> Approved-by: Michel Dänzer <mdaenzer@redhat.com> Approved-by: Eric Chanudet <echanude@redhat.com> Signed-off-by: Jan Stancek <jstancek@redhat.com>
2 parents f58fc75 + 16f3351 commit 26edd1d

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19 files changed

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19 files changed

+299
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lines changed

‎arch/Kconfig‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1370,6 +1370,9 @@ config ARCH_HAS_ELFCORE_COMPAT
13701370
config ARCH_HAS_PARANOID_L1D_FLUSH
13711371
bool
13721372

1373+
config ARCH_HAVE_TRACE_MMIO_ACCESS
1374+
bool
1375+
13731376
config DYNAMIC_SIGFRAME
13741377
bool
13751378

‎arch/arm64/Kconfig‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,7 @@ config ARM64
4949
select ARCH_HAS_ZONE_DMA_SET if EXPERT
5050
select ARCH_HAVE_ELF_PROT
5151
select ARCH_HAVE_NMI_SAFE_CMPXCHG
52+
select ARCH_HAVE_TRACE_MMIO_ACCESS
5253
select ARCH_INLINE_READ_LOCK if !PREEMPTION
5354
select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
5455
select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION

‎arch/arm64/include/asm/io.h‎

Lines changed: 8 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
9191
}
9292

9393
/* IO barriers */
94-
#define __iormb(v) \
94+
#define __io_ar(v) \
9595
({ \
9696
unsigned long tmp; \
9797
\
@@ -108,39 +108,14 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
108108
: "memory"); \
109109
})
110110

111-
#define __io_par(v) __iormb(v)
112-
#define __iowmb() dma_wmb()
113-
#define __iomb() dma_mb()
114-
115-
/*
116-
* Relaxed I/O memory access primitives. These follow the Device memory
117-
* ordering rules but do not guarantee any ordering relative to Normal memory
118-
* accesses.
119-
*/
120-
#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
121-
#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
122-
#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
123-
#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
111+
#define __io_bw() dma_wmb()
112+
#define __io_br(v)
113+
#define __io_aw(v)
124114

125-
#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c)))
126-
#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
127-
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
128-
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
129-
130-
/*
131-
* I/O memory access primitives. Reads are ordered relative to any
132-
* following Normal memory access. Writes are ordered relative to any prior
133-
* Normal memory access.
134-
*/
135-
#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(__v); __v; })
136-
#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(__v); __v; })
137-
#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(__v); __v; })
138-
#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(__v); __v; })
139-
140-
#define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); })
141-
#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); })
142-
#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); })
143-
#define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c)); })
115+
/* arm64-specific, don't use in portable drivers */
116+
#define __iormb(v) __io_ar(v)
117+
#define __iowmb() __io_bw()
118+
#define __iomb() dma_mb()
144119

145120
/*
146121
* I/O port access primitives.

‎drivers/gpu/drm/meson/meson_viu.c‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -468,17 +468,17 @@ void meson_viu_init(struct meson_drm *priv)
468468
priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE));
469469

470470
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
471-
writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) |
472-
VIU_OSD_BLEND_REORDER(1, 0) |
473-
VIU_OSD_BLEND_REORDER(2, 0) |
474-
VIU_OSD_BLEND_REORDER(3, 0) |
475-
VIU_OSD_BLEND_DIN_EN(1) |
476-
VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 |
477-
VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 |
478-
VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 |
479-
VIU_OSD_BLEND_BLEN2_PREMULT_EN(1) |
480-
VIU_OSD_BLEND_HOLD_LINES(4),
481-
priv->io_base + _REG(VIU_OSD_BLEND_CTRL));
471+
u32 val = (u32)VIU_OSD_BLEND_REORDER(0, 1) |
472+
(u32)VIU_OSD_BLEND_REORDER(1, 0) |
473+
(u32)VIU_OSD_BLEND_REORDER(2, 0) |
474+
(u32)VIU_OSD_BLEND_REORDER(3, 0) |
475+
(u32)VIU_OSD_BLEND_DIN_EN(1) |
476+
(u32)VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 |
477+
(u32)VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 |
478+
(u32)VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 |
479+
(u32)VIU_OSD_BLEND_BLEN2_PREMULT_EN(1) |
480+
(u32)VIU_OSD_BLEND_HOLD_LINES(4);
481+
writel_relaxed(val, priv->io_base + _REG(VIU_OSD_BLEND_CTRL));
482482

483483
writel_relaxed(OSD_BLEND_PATH_SEL_ENABLE,
484484
priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));

‎drivers/hwtracing/coresight/coresight-etm4x-core.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -99,15 +99,15 @@ u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
9999
}
100100

101101
if (!_relaxed)
102-
__iormb(res); /* Imitate the !relaxed I/O helpers */
102+
__io_ar(res); /* Imitate the !relaxed I/O helpers */
103103

104104
return res;
105105
}
106106

107107
void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
108108
{
109109
if (!_relaxed)
110-
__iowmb(); /* Imitate the !relaxed I/O helpers */
110+
__io_bw(); /* Imitate the !relaxed I/O helpers */
111111
if (!_64bit)
112112
val &= GENMASK(31, 0);
113113

@@ -131,15 +131,15 @@ static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
131131
}
132132

133133
if (!_relaxed)
134-
__iormb(res); /* Imitate the !relaxed I/O helpers */
134+
__io_ar(res); /* Imitate the !relaxed I/O helpers */
135135

136136
return res;
137137
}
138138

139139
static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
140140
{
141141
if (!_relaxed)
142-
__iowmb(); /* Imitate the !relaxed I/O helpers */
142+
__io_bw(); /* Imitate the !relaxed I/O helpers */
143143
if (!_64bit)
144144
val &= GENMASK(31, 0);
145145

‎drivers/hwtracing/coresight/coresight-etm4x.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -448,14 +448,14 @@
448448
#define etm4x_read32(csa, offset) \
449449
({ \
450450
u32 __val = etm4x_relaxed_read32((csa), (offset)); \
451-
__iormb(__val); \
451+
__io_ar(__val); \
452452
__val; \
453453
})
454454

455455
#define etm4x_read64(csa, offset) \
456456
({ \
457457
u64 __val = etm4x_relaxed_read64((csa), (offset)); \
458-
__iormb(__val); \
458+
__io_ar(__val); \
459459
__val; \
460460
})
461461

@@ -479,13 +479,13 @@
479479

480480
#define etm4x_write32(csa, val, offset) \
481481
do { \
482-
__iowmb(); \
482+
__io_bw(); \
483483
etm4x_relaxed_write32((csa), (val), (offset)); \
484484
} while (0)
485485

486486
#define etm4x_write64(csa, val, offset) \
487487
do { \
488-
__iowmb(); \
488+
__io_bw(); \
489489
etm4x_relaxed_write64((csa), (val), (offset)); \
490490
} while (0)
491491

‎drivers/irqchip/irq-tegra.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -148,10 +148,10 @@ static int tegra_ictlr_suspend(void)
148148
lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
149149

150150
/* Disable COP interrupts */
151-
writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
151+
writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);
152152

153153
/* Disable CPU interrupts */
154-
writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
154+
writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);
155155

156156
/* Enable the wakeup sources of ictlr */
157157
writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
@@ -172,12 +172,12 @@ static void tegra_ictlr_resume(void)
172172

173173
writel_relaxed(lic->cpu_iep[i],
174174
ictlr + ICTLR_CPU_IEP_CLASS);
175-
writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
175+
writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);
176176
writel_relaxed(lic->cpu_ier[i],
177177
ictlr + ICTLR_CPU_IER_SET);
178178
writel_relaxed(lic->cop_iep[i],
179179
ictlr + ICTLR_COP_IEP_CLASS);
180-
writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
180+
writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);
181181
writel_relaxed(lic->cop_ier[i],
182182
ictlr + ICTLR_COP_IER_SET);
183183
}
@@ -312,7 +312,7 @@ static int __init tegra_ictlr_init(struct device_node *node,
312312
lic->base[i] = base;
313313

314314
/* Disable all interrupts */
315-
writel_relaxed(~0UL, base + ICTLR_CPU_IER_CLR);
315+
writel_relaxed(GENMASK(31, 0), base + ICTLR_CPU_IER_CLR);
316316
/* All interrupts target IRQ */
317317
writel_relaxed(0, base + ICTLR_CPU_IEP_CLASS);
318318

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