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accel/amdxdna: Add RyzenAI-npu6 support
Add NPU6 registers and other private configurations. Co-developed-by: Xiaoming Ren <xiaoming.ren@amd.com> Signed-off-by: Xiaoming Ren <xiaoming.ren@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241213232933.1545388-2-lizhi.hou@amd.com
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‎drivers/accel/amdxdna/Makefile‎

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@@ -17,5 +17,6 @@ amdxdna-y := \
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npu1_regs.o \
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npu2_regs.o \
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npu4_regs.o \
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npu5_regs.o
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npu5_regs.o \
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npu6_regs.o
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obj-$(CONFIG_DRM_ACCEL_AMDXDNA) = amdxdna.o

‎drivers/accel/amdxdna/amdxdna_pci_drv.c‎

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@@ -39,6 +39,7 @@ static const struct amdxdna_device_id amdxdna_ids[] = {
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{ 0x17f0, 0x0, &dev_npu2_info },
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{ 0x17f0, 0x10, &dev_npu4_info },
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{ 0x17f0, 0x11, &dev_npu5_info },
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{ 0x17f0, 0x20, &dev_npu6_info },
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{0}
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};
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‎drivers/accel/amdxdna/amdxdna_pci_drv.h‎

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@@ -116,6 +116,7 @@ extern const struct amdxdna_dev_info dev_npu1_info;
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extern const struct amdxdna_dev_info dev_npu2_info;
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extern const struct amdxdna_dev_info dev_npu4_info;
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extern const struct amdxdna_dev_info dev_npu5_info;
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extern const struct amdxdna_dev_info dev_npu6_info;
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int amdxdna_sysfs_init(struct amdxdna_dev *xdna);
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void amdxdna_sysfs_fini(struct amdxdna_dev *xdna);

‎drivers/accel/amdxdna/npu6_regs.c‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2024, Advanced Micro Devices, Inc.
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*/
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#include <drm/amdxdna_accel.h>
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#include <drm/drm_device.h>
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#include <drm/gpu_scheduler.h>
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#include <linux/sizes.h>
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#include "aie2_pci.h"
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#include "amdxdna_mailbox.h"
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#include "amdxdna_pci_drv.h"
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/* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */
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#define MPNPU_PUB_SEC_INTR 0x3010060
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#define MPNPU_PUB_PWRMGMT_INTR 0x3010064
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#define MPNPU_PUB_SCRATCH0 0x301006C
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#define MPNPU_PUB_SCRATCH1 0x3010070
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#define MPNPU_PUB_SCRATCH2 0x3010074
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#define MPNPU_PUB_SCRATCH3 0x3010078
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#define MPNPU_PUB_SCRATCH4 0x301007C
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#define MPNPU_PUB_SCRATCH5 0x3010080
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#define MPNPU_PUB_SCRATCH6 0x3010084
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#define MPNPU_PUB_SCRATCH7 0x3010088
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#define MPNPU_PUB_SCRATCH8 0x301008C
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#define MPNPU_PUB_SCRATCH9 0x3010090
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#define MPNPU_PUB_SCRATCH10 0x3010094
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#define MPNPU_PUB_SCRATCH11 0x3010098
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#define MPNPU_PUB_SCRATCH12 0x301009C
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#define MPNPU_PUB_SCRATCH13 0x30100A0
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#define MPNPU_PUB_SCRATCH14 0x30100A4
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#define MPNPU_PUB_SCRATCH15 0x30100A8
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#define MP0_C2PMSG_73 0x3810A24
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#define MP0_C2PMSG_123 0x3810AEC
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#define MP1_C2PMSG_0 0x3B10900
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#define MP1_C2PMSG_60 0x3B109F0
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#define MP1_C2PMSG_61 0x3B109F4
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#define MPNPU_SRAM_X2I_MAILBOX_0 0x3600000
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#define MPNPU_SRAM_X2I_MAILBOX_15 0x361E000
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#define MPNPU_SRAM_X2I_MAILBOX_31 0x363E000
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#define MPNPU_SRAM_I2X_MAILBOX_31 0x363F000
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#define MMNPU_APERTURE0_BASE 0x3000000
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#define MMNPU_APERTURE1_BASE 0x3600000
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#define MMNPU_APERTURE3_BASE 0x3810000
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#define MMNPU_APERTURE4_BASE 0x3B10000
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/* PCIe BAR Index for NPU6 */
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#define NPU6_REG_BAR_INDEX 0
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#define NPU6_MBOX_BAR_INDEX 0
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#define NPU6_PSP_BAR_INDEX 4
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#define NPU6_SMU_BAR_INDEX 5
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#define NPU6_SRAM_BAR_INDEX 2
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/* Associated BARs and Apertures */
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#define NPU6_REG_BAR_BASE MMNPU_APERTURE0_BASE
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#define NPU6_MBOX_BAR_BASE MMNPU_APERTURE0_BASE
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#define NPU6_PSP_BAR_BASE MMNPU_APERTURE3_BASE
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#define NPU6_SMU_BAR_BASE MMNPU_APERTURE4_BASE
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#define NPU6_SRAM_BAR_BASE MMNPU_APERTURE1_BASE
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#define NPU6_RT_CFG_TYPE_PDI_LOAD 5
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#define NPU6_RT_CFG_TYPE_DEBUG_BO 10
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#define NPU6_RT_CFG_VAL_PDI_LOAD_MGMT 0
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#define NPU6_RT_CFG_VAL_PDI_LOAD_APP 1
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#define NPU6_RT_CFG_VAL_DEBUG_BO_DEFAULT 0
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#define NPU6_RT_CFG_VAL_DEBUG_BO_LARGE 1
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#define NPU6_MPNPUCLK_FREQ_MAX 1267
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#define NPU6_HCLK_FREQ_MAX 1800
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const struct amdxdna_dev_priv npu6_dev_priv = {
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.fw_path = "amdnpu/17f0_10/npu.sbin",
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.protocol_major = 0x6,
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.protocol_minor = 12,
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.rt_config = {NPU6_RT_CFG_TYPE_PDI_LOAD, NPU6_RT_CFG_VAL_PDI_LOAD_APP},
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.col_align = COL_ALIGN_NATURE,
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.mbox_dev_addr = NPU6_MBOX_BAR_BASE,
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.mbox_size = 0, /* Use BAR size */
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.sram_dev_addr = NPU6_SRAM_BAR_BASE,
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.sram_offs = {
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DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
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DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),
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},
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.psp_regs_off = {
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DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU6_PSP, MP0_C2PMSG_123),
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DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU6_REG, MPNPU_PUB_SCRATCH3),
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DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU6_REG, MPNPU_PUB_SCRATCH4),
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DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU6_REG, MPNPU_PUB_SCRATCH9),
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DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU6_PSP, MP0_C2PMSG_73),
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DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU6_PSP, MP0_C2PMSG_123),
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DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU6_REG, MPNPU_PUB_SCRATCH3),
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},
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.smu_regs_off = {
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DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU6_SMU, MP1_C2PMSG_0),
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DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU6_SMU, MP1_C2PMSG_60),
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DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU6_SMU, MMNPU_APERTURE4_BASE),
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DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU6_SMU, MP1_C2PMSG_61),
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DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU6_SMU, MP1_C2PMSG_60),
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},
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};
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const struct amdxdna_dev_info dev_npu6_info = {
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.reg_bar = NPU6_REG_BAR_INDEX,
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.mbox_bar = NPU6_MBOX_BAR_INDEX,
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.sram_bar = NPU6_SRAM_BAR_INDEX,
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.psp_bar = NPU6_PSP_BAR_INDEX,
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.smu_bar = NPU6_SMU_BAR_INDEX,
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.first_col = 0,
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.dev_mem_buf_shift = 15, /* 32 KiB aligned */
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.dev_mem_base = AIE2_DEVM_BASE,
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.dev_mem_size = AIE2_DEVM_SIZE,
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.vbnv = "RyzenAI-npu6",
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.device_type = AMDXDNA_DEV_TYPE_KMQ,
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.dev_priv = &npu6_dev_priv,
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.ops = &aie2_ops,
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};

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