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ASoC: Intel: avs: Implement CLDMA transfer
SKL and KBL rely on a dedicated HDAudio DMA stream for code loading and authentication. The implementation of this specific mechanism for SKL-based platforms re-uses HDAudio DMA (streaming) functions found in HDA library to avoid duplication of functionality. Signed-off-by: Amadeusz Sławiński <amadeuszx.slawinski@linux.intel.com> Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com> Link: https://lore.kernel.org/r/20220311153544.136854-16-cezary.rojewski@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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‎sound/soc/intel/avs/Makefile‎

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# SPDX-License-Identifier: GPL-2.0-only
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snd-soc-avs-objs := dsp.o ipc.o messages.o utils.o core.o loader.o
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snd-soc-avs-objs += cldma.o
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obj-$(CONFIG_SND_SOC_INTEL_AVS) += snd-soc-avs.o

‎sound/soc/intel/avs/cldma.c‎

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// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
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//
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// Author: Cezary Rojewski <cezary.rojewski@intel.com>
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//
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#include <linux/pci.h>
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#include <sound/hda_register.h>
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#include <sound/hdaudio_ext.h>
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#include "cldma.h"
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#include "registers.h"
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/* Stream Registers */
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#define AZX_CL_SD_BASE 0x80
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#define AZX_SD_CTL_STRM_MASK GENMASK(23, 20)
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#define AZX_SD_CTL_STRM(s) (((s)->stream_tag << 20) & AZX_SD_CTL_STRM_MASK)
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#define AZX_SD_BDLPL_BDLPLBA_MASK GENMASK(31, 7)
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#define AZX_SD_BDLPL_BDLPLBA(lb) ((lb) & AZX_SD_BDLPL_BDLPLBA_MASK)
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/* Software Position Based FIFO Capability Registers */
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#define AZX_CL_SPBFCS 0x20
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#define AZX_REG_CL_SPBFCTL (AZX_CL_SPBFCS + 0x4)
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#define AZX_REG_CL_SD_SPIB (AZX_CL_SPBFCS + 0x8)
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#define AVS_CL_OP_INTERVAL_US 3
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#define AVS_CL_OP_TIMEOUT_US 300
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#define AVS_CL_IOC_TIMEOUT_MS 300
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#define AVS_CL_STREAM_INDEX 0
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struct hda_cldma {
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struct device *dev;
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struct hdac_bus *bus;
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void __iomem *dsp_ba;
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unsigned int buffer_size;
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unsigned int num_periods;
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unsigned int stream_tag;
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void __iomem *sd_addr;
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struct snd_dma_buffer dmab_data;
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struct snd_dma_buffer dmab_bdl;
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struct delayed_work memcpy_work;
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struct completion completion;
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/* runtime */
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void *position;
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unsigned int remaining;
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unsigned int sd_status;
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};
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static void cldma_memcpy_work(struct work_struct *work);
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struct hda_cldma code_loader = {
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.stream_tag = AVS_CL_STREAM_INDEX + 1,
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.memcpy_work = __DELAYED_WORK_INITIALIZER(code_loader.memcpy_work, cldma_memcpy_work, 0),
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.completion = COMPLETION_INITIALIZER(code_loader.completion),
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};
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void hda_cldma_fill(struct hda_cldma *cl)
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{
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unsigned int size, offset;
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if (cl->remaining > cl->buffer_size)
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size = cl->buffer_size;
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else
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size = cl->remaining;
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offset = snd_hdac_stream_readl(cl, CL_SD_SPIB);
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if (offset + size > cl->buffer_size) {
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unsigned int ss;
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ss = cl->buffer_size - offset;
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memcpy(cl->dmab_data.area + offset, cl->position, ss);
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offset = 0;
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size -= ss;
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cl->position += ss;
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cl->remaining -= ss;
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}
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memcpy(cl->dmab_data.area + offset, cl->position, size);
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cl->position += size;
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cl->remaining -= size;
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snd_hdac_stream_writel(cl, CL_SD_SPIB, offset + size);
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}
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static void cldma_memcpy_work(struct work_struct *work)
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{
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struct hda_cldma *cl = container_of(work, struct hda_cldma, memcpy_work.work);
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int ret;
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ret = hda_cldma_start(cl);
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if (ret < 0) {
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dev_err(cl->dev, "cldma set RUN failed: %d\n", ret);
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return;
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}
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while (true) {
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ret = wait_for_completion_timeout(&cl->completion,
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msecs_to_jiffies(AVS_CL_IOC_TIMEOUT_MS));
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if (!ret) {
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dev_err(cl->dev, "cldma IOC timeout\n");
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break;
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}
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if (!(cl->sd_status & SD_INT_COMPLETE)) {
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dev_err(cl->dev, "cldma transfer error, SD status: 0x%08x\n",
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cl->sd_status);
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break;
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}
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if (!cl->remaining)
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break;
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reinit_completion(&cl->completion);
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hda_cldma_fill(cl);
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/* enable CLDMA interrupt */
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snd_hdac_adsp_updatel(cl, AVS_ADSP_REG_ADSPIC, AVS_ADSP_ADSPIC_CLDMA,
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AVS_ADSP_ADSPIC_CLDMA);
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}
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}
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void hda_cldma_transfer(struct hda_cldma *cl, unsigned long start_delay)
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{
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if (!cl->remaining)
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return;
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reinit_completion(&cl->completion);
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/* fill buffer with the first chunk before scheduling run */
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hda_cldma_fill(cl);
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schedule_delayed_work(&cl->memcpy_work, start_delay);
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}
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int hda_cldma_start(struct hda_cldma *cl)
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{
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unsigned int reg;
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/* enable interrupts */
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snd_hdac_adsp_updatel(cl, AVS_ADSP_REG_ADSPIC, AVS_ADSP_ADSPIC_CLDMA,
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AVS_ADSP_ADSPIC_CLDMA);
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snd_hdac_stream_updateb(cl, SD_CTL, SD_INT_MASK | SD_CTL_DMA_START,
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SD_INT_MASK | SD_CTL_DMA_START);
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/* await DMA engine start */
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return snd_hdac_stream_readb_poll(cl, SD_CTL, reg, reg & SD_CTL_DMA_START,
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AVS_CL_OP_INTERVAL_US, AVS_CL_OP_TIMEOUT_US);
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}
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int hda_cldma_stop(struct hda_cldma *cl)
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{
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unsigned int reg;
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int ret;
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/* disable interrupts */
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snd_hdac_adsp_updatel(cl, AVS_ADSP_REG_ADSPIC, AVS_ADSP_ADSPIC_CLDMA, 0);
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snd_hdac_stream_updateb(cl, SD_CTL, SD_INT_MASK | SD_CTL_DMA_START, 0);
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/* await DMA engine stop */
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ret = snd_hdac_stream_readb_poll(cl, SD_CTL, reg, !(reg & SD_CTL_DMA_START),
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AVS_CL_OP_INTERVAL_US, AVS_CL_OP_TIMEOUT_US);
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cancel_delayed_work_sync(&cl->memcpy_work);
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return ret;
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}
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int hda_cldma_reset(struct hda_cldma *cl)
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{
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unsigned int reg;
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int ret;
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ret = hda_cldma_stop(cl);
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if (ret < 0) {
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dev_err(cl->dev, "cldma stop failed: %d\n", ret);
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return ret;
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}
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snd_hdac_stream_updateb(cl, SD_CTL, 1, 1);
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ret = snd_hdac_stream_readb_poll(cl, SD_CTL, reg, (reg & 1), AVS_CL_OP_INTERVAL_US,
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AVS_CL_OP_TIMEOUT_US);
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if (ret < 0) {
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dev_err(cl->dev, "cldma set SRST failed: %d\n", ret);
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return ret;
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}
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snd_hdac_stream_updateb(cl, SD_CTL, 1, 0);
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ret = snd_hdac_stream_readb_poll(cl, SD_CTL, reg, !(reg & 1), AVS_CL_OP_INTERVAL_US,
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AVS_CL_OP_TIMEOUT_US);
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if (ret < 0) {
191+
dev_err(cl->dev, "cldma unset SRST failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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void hda_cldma_set_data(struct hda_cldma *cl, void *data, unsigned int size)
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{
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/* setup runtime */
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cl->position = data;
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cl->remaining = size;
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}
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static void cldma_setup_bdle(struct hda_cldma *cl, u32 bdle_size)
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{
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struct snd_dma_buffer *dmab = &cl->dmab_data;
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__le32 *bdl = (__le32 *)cl->dmab_bdl.area;
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int remaining = cl->buffer_size;
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int offset = 0;
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cl->num_periods = 0;
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while (remaining > 0) {
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phys_addr_t addr;
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int chunk;
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addr = snd_sgbuf_get_addr(dmab, offset);
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bdl[0] = cpu_to_le32(lower_32_bits(addr));
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bdl[1] = cpu_to_le32(upper_32_bits(addr));
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chunk = snd_sgbuf_get_chunk_size(dmab, offset, bdle_size);
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bdl[2] = cpu_to_le32(chunk);
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remaining -= chunk;
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/* set IOC only for the last entry */
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bdl[3] = (remaining > 0) ? 0 : cpu_to_le32(0x01);
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bdl += 4;
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offset += chunk;
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cl->num_periods++;
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}
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}
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void hda_cldma_setup(struct hda_cldma *cl)
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{
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dma_addr_t bdl_addr = cl->dmab_bdl.addr;
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cldma_setup_bdle(cl, cl->buffer_size / 2);
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snd_hdac_stream_writel(cl, SD_BDLPL, AZX_SD_BDLPL_BDLPLBA(lower_32_bits(bdl_addr)));
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snd_hdac_stream_writel(cl, SD_BDLPU, upper_32_bits(bdl_addr));
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snd_hdac_stream_writel(cl, SD_CBL, cl->buffer_size);
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snd_hdac_stream_writeb(cl, SD_LVI, cl->num_periods - 1);
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snd_hdac_stream_updatel(cl, SD_CTL, AZX_SD_CTL_STRM_MASK, AZX_SD_CTL_STRM(cl));
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/* enable spib */
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snd_hdac_stream_writel(cl, CL_SPBFCTL, 1);
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}
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static irqreturn_t cldma_irq_handler(int irq, void *dev_id)
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{
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struct hda_cldma *cl = dev_id;
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u32 adspis;
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adspis = snd_hdac_adsp_readl(cl, AVS_ADSP_REG_ADSPIS);
257+
if (adspis == UINT_MAX)
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return IRQ_NONE;
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if (!(adspis & AVS_ADSP_ADSPIS_CLDMA))
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return IRQ_NONE;
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cl->sd_status = snd_hdac_stream_readb(cl, SD_STS);
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dev_warn(cl->dev, "%s sd_status: 0x%08x\n", __func__, cl->sd_status);
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/* disable CLDMA interrupt */
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snd_hdac_adsp_updatel(cl, AVS_ADSP_REG_ADSPIC, AVS_ADSP_ADSPIC_CLDMA, 0);
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complete(&cl->completion);
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return IRQ_HANDLED;
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}
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int hda_cldma_init(struct hda_cldma *cl, struct hdac_bus *bus, void __iomem *dsp_ba,
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unsigned int buffer_size)
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{
276+
struct pci_dev *pci = to_pci_dev(bus->dev);
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int ret;
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ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev, buffer_size, &cl->dmab_data);
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if (ret < 0)
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return ret;
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ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, bus->dev, BDL_SIZE, &cl->dmab_bdl);
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if (ret < 0)
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goto alloc_err;
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cl->dev = bus->dev;
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cl->bus = bus;
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cl->dsp_ba = dsp_ba;
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cl->buffer_size = buffer_size;
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cl->sd_addr = dsp_ba + AZX_CL_SD_BASE;
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ret = pci_request_irq(pci, 0, cldma_irq_handler, NULL, cl, "CLDMA");
294+
if (ret < 0) {
295+
dev_err(cl->dev, "Failed to request CLDMA IRQ handler: %d\n", ret);
296+
goto req_err;
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}
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return 0;
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req_err:
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snd_dma_free_pages(&cl->dmab_bdl);
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alloc_err:
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snd_dma_free_pages(&cl->dmab_data);
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return ret;
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}
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void hda_cldma_free(struct hda_cldma *cl)
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{
311+
struct pci_dev *pci = to_pci_dev(cl->dev);
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pci_free_irq(pci, 0, cl);
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snd_dma_free_pages(&cl->dmab_data);
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snd_dma_free_pages(&cl->dmab_bdl);
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}

‎sound/soc/intel/avs/cldma.h‎

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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
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*
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* Author: Cezary Rojewski <cezary.rojewski@intel.com>
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*/
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#ifndef __SOUND_SOC_INTEL_AVS_CLDMA_H
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#define __SOUND_SOC_INTEL_AVS_CLDMA_H
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#define AVS_CL_DEFAULT_BUFFER_SIZE (32 * PAGE_SIZE)
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struct hda_cldma;
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extern struct hda_cldma code_loader;
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void hda_cldma_fill(struct hda_cldma *cl);
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void hda_cldma_transfer(struct hda_cldma *cl, unsigned long start_delay);
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int hda_cldma_start(struct hda_cldma *cl);
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int hda_cldma_stop(struct hda_cldma *cl);
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int hda_cldma_reset(struct hda_cldma *cl);
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void hda_cldma_set_data(struct hda_cldma *cl, void *data, unsigned int size);
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void hda_cldma_setup(struct hda_cldma *cl);
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int hda_cldma_init(struct hda_cldma *cl, struct hdac_bus *bus, void __iomem *dsp_ba,
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unsigned int buffer_size);
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void hda_cldma_free(struct hda_cldma *cl);
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#endif

‎sound/soc/intel/avs/registers.h‎

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#define AVS_ADSP_REG_ADSPIS (AVS_ADSP_GEN_BASE + 0x0C)
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2424
#define AVS_ADSP_ADSPIC_IPC BIT(0)
25+
#define AVS_ADSP_ADSPIC_CLDMA BIT(1)
2526
#define AVS_ADSP_ADSPIS_IPC BIT(0)
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#define AVS_ADSP_ADSPIS_CLDMA BIT(1)
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2729
#define AVS_ADSPCS_CRST_MASK(cm) (cm)
2830
#define AVS_ADSPCS_CSTALL_MASK(cm) ((cm) << 8)

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