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StanleyYP Wangnbd168
StanleyYP Wang
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nbd168
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wifi: mt76: mt7996: rework register offsets for mt7992
Add mt7992_offs to differentiate registers that share the same definitions with mt7996 chipsets but have differnet offsets. This is a preliminary patch for mt7992 chipsets support. Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com> Signed-off-by: Shayne Chen <shayne.chen@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
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-23
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‎drivers/net/wireless/mediatek/mt76/mt7996/mmio.c‎

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,58 @@ static const struct __base mt7996_reg_base[] = {
3030
[WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } },
3131
};
3232

33+
static const u32 mt7996_offs[] = {
34+
[MIB_RVSR0] = 0x720,
35+
[MIB_RVSR1] = 0x724,
36+
[MIB_BTSCR5] = 0x788,
37+
[MIB_BTSCR6] = 0x798,
38+
[MIB_RSCR1] = 0x7ac,
39+
[MIB_RSCR27] = 0x954,
40+
[MIB_RSCR28] = 0x958,
41+
[MIB_RSCR29] = 0x95c,
42+
[MIB_RSCR30] = 0x960,
43+
[MIB_RSCR31] = 0x964,
44+
[MIB_RSCR33] = 0x96c,
45+
[MIB_RSCR35] = 0x974,
46+
[MIB_RSCR36] = 0x978,
47+
[MIB_BSCR0] = 0x9cc,
48+
[MIB_BSCR1] = 0x9d0,
49+
[MIB_BSCR2] = 0x9d4,
50+
[MIB_BSCR3] = 0x9d8,
51+
[MIB_BSCR4] = 0x9dc,
52+
[MIB_BSCR5] = 0x9e0,
53+
[MIB_BSCR6] = 0x9e4,
54+
[MIB_BSCR7] = 0x9e8,
55+
[MIB_BSCR17] = 0xa10,
56+
[MIB_TRDR1] = 0xa28,
57+
};
58+
59+
static const u32 mt7992_offs[] = {
60+
[MIB_RVSR0] = 0x760,
61+
[MIB_RVSR1] = 0x764,
62+
[MIB_BTSCR5] = 0x7c8,
63+
[MIB_BTSCR6] = 0x7d8,
64+
[MIB_RSCR1] = 0x7f0,
65+
[MIB_RSCR27] = 0x998,
66+
[MIB_RSCR28] = 0x99c,
67+
[MIB_RSCR29] = 0x9a0,
68+
[MIB_RSCR30] = 0x9a4,
69+
[MIB_RSCR31] = 0x9a8,
70+
[MIB_RSCR33] = 0x9b0,
71+
[MIB_RSCR35] = 0x9b8,
72+
[MIB_RSCR36] = 0x9bc,
73+
[MIB_BSCR0] = 0xac8,
74+
[MIB_BSCR1] = 0xacc,
75+
[MIB_BSCR2] = 0xad0,
76+
[MIB_BSCR3] = 0xad4,
77+
[MIB_BSCR4] = 0xad8,
78+
[MIB_BSCR5] = 0xadc,
79+
[MIB_BSCR6] = 0xae0,
80+
[MIB_BSCR7] = 0xae4,
81+
[MIB_BSCR17] = 0xb0c,
82+
[MIB_TRDR1] = 0xb24,
83+
};
84+
3385
static const struct __map mt7996_reg_map[] = {
3486
{ 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
3587
{ 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
@@ -382,6 +434,13 @@ static int mt7996_mmio_init(struct mt76_dev *mdev,
382434
switch (device_id) {
383435
case 0x7990:
384436
dev->reg.base = mt7996_reg_base;
437+
dev->reg.offs_rev = mt7996_offs;
438+
dev->reg.map = mt7996_reg_map;
439+
dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map);
440+
break;
441+
case 0x7992:
442+
dev->reg.base = mt7996_reg_base;
443+
dev->reg.offs_rev = mt7992_offs;
385444
dev->reg.map = mt7996_reg_map;
386445
dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map);
387446
break;

‎drivers/net/wireless/mediatek/mt76/mt7996/regs.h‎

Lines changed: 53 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@ struct __base {
1919
/* used to differentiate between generations */
2020
struct mt7996_reg_desc {
2121
const struct __base *base;
22+
const u32 *offs_rev;
2223
const struct __map *map;
2324
u32 map_size;
2425
};
@@ -39,6 +40,35 @@ enum base_rev {
3940

4041
#define __BASE(_id, _band) (dev->reg.base[(_id)].band_base[(_band)])
4142

43+
enum offs_rev {
44+
MIB_RVSR0,
45+
MIB_RVSR1,
46+
MIB_BTSCR5,
47+
MIB_BTSCR6,
48+
MIB_RSCR1,
49+
MIB_RSCR27,
50+
MIB_RSCR28,
51+
MIB_RSCR29,
52+
MIB_RSCR30,
53+
MIB_RSCR31,
54+
MIB_RSCR33,
55+
MIB_RSCR35,
56+
MIB_RSCR36,
57+
MIB_BSCR0,
58+
MIB_BSCR1,
59+
MIB_BSCR2,
60+
MIB_BSCR3,
61+
MIB_BSCR4,
62+
MIB_BSCR5,
63+
MIB_BSCR6,
64+
MIB_BSCR7,
65+
MIB_BSCR17,
66+
MIB_TRDR1,
67+
__MT_OFFS_MAX,
68+
};
69+
70+
#define __OFFS(id) (dev->reg.offs_rev[(id)])
71+
4272
/* RRO TOP */
4373
#define MT_RRO_TOP_BASE 0xA000
4474
#define MT_RRO_TOP(ofs) (MT_RRO_TOP_BASE + (ofs))
@@ -178,32 +208,32 @@ enum base_rev {
178208
#define MT_WF_MIB_BASE(_band) __BASE(WF_MIB_BASE, (_band))
179209
#define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs))
180210

181-
#define MT_MIB_BSCR0(_band) MT_WF_MIB(_band, 0x9cc)
182-
#define MT_MIB_BSCR1(_band) MT_WF_MIB(_band, 0x9d0)
183-
#define MT_MIB_BSCR2(_band) MT_WF_MIB(_band, 0x9d4)
184-
#define MT_MIB_BSCR3(_band) MT_WF_MIB(_band, 0x9d8)
185-
#define MT_MIB_BSCR4(_band) MT_WF_MIB(_band, 0x9dc)
186-
#define MT_MIB_BSCR5(_band) MT_WF_MIB(_band, 0x9e0)
187-
#define MT_MIB_BSCR6(_band) MT_WF_MIB(_band, 0x9e4)
188-
#define MT_MIB_BSCR7(_band) MT_WF_MIB(_band, 0x9e8)
189-
#define MT_MIB_BSCR17(_band) MT_WF_MIB(_band, 0xa10)
211+
#define MT_MIB_BSCR0(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR0))
212+
#define MT_MIB_BSCR1(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR1))
213+
#define MT_MIB_BSCR2(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR2))
214+
#define MT_MIB_BSCR3(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR3))
215+
#define MT_MIB_BSCR4(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR4))
216+
#define MT_MIB_BSCR5(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR5))
217+
#define MT_MIB_BSCR6(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR6))
218+
#define MT_MIB_BSCR7(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR7))
219+
#define MT_MIB_BSCR17(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR17))
190220

191221
#define MT_MIB_TSCR5(_band) MT_WF_MIB(_band, 0x6c4)
192222
#define MT_MIB_TSCR6(_band) MT_WF_MIB(_band, 0x6c8)
193223
#define MT_MIB_TSCR7(_band) MT_WF_MIB(_band, 0x6d0)
194224

195-
#define MT_MIB_RSCR1(_band) MT_WF_MIB(_band, 0x7ac)
225+
#define MT_MIB_RSCR1(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR1))
196226
/* rx mpdu counter, full 32 bits */
197-
#define MT_MIB_RSCR31(_band) MT_WF_MIB(_band, 0x964)
198-
#define MT_MIB_RSCR33(_band) MT_WF_MIB(_band, 0x96c)
227+
#define MT_MIB_RSCR31(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR31))
228+
#define MT_MIB_RSCR33(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR33))
199229

200230
#define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020)
201231
#define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0)
202232

203-
#define MT_MIB_RVSR0(_band) MT_WF_MIB(_band, 0x720)
233+
#define MT_MIB_RVSR0(_band) MT_WF_MIB(_band, __OFFS(MIB_RVSR0))
204234

205-
#define MT_MIB_RSCR35(_band) MT_WF_MIB(_band, 0x974)
206-
#define MT_MIB_RSCR36(_band) MT_WF_MIB(_band, 0x978)
235+
#define MT_MIB_RSCR35(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR35))
236+
#define MT_MIB_RSCR36(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR36))
207237

208238
/* tx ampdu cnt, full 32 bits */
209239
#define MT_MIB_TSCR0(_band) MT_WF_MIB(_band, 0x6b0)
@@ -216,16 +246,16 @@ enum base_rev {
216246
#define MT_MIB_TSCR4(_band) MT_WF_MIB(_band, 0x6c0)
217247

218248
/* rx ampdu count, 32-bit */
219-
#define MT_MIB_RSCR27(_band) MT_WF_MIB(_band, 0x954)
249+
#define MT_MIB_RSCR27(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR27))
220250

221251
/* rx ampdu bytes count, 32-bit */
222-
#define MT_MIB_RSCR28(_band) MT_WF_MIB(_band, 0x958)
252+
#define MT_MIB_RSCR28(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR28))
223253

224254
/* rx ampdu valid subframe count */
225-
#define MT_MIB_RSCR29(_band) MT_WF_MIB(_band, 0x95c)
255+
#define MT_MIB_RSCR29(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR29))
226256

227257
/* rx ampdu valid subframe bytes count, 32bits */
228-
#define MT_MIB_RSCR30(_band) MT_WF_MIB(_band, 0x960)
258+
#define MT_MIB_RSCR30(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR30))
229259

230260
/* remaining windows protected stats */
231261
#define MT_MIB_SDR27(_band) MT_WF_MIB(_band, 0x080)
@@ -234,18 +264,18 @@ enum base_rev {
234264
#define MT_MIB_SDR28(_band) MT_WF_MIB(_band, 0x084)
235265
#define MT_MIB_SDR28_TX_RWP_NEED_CNT GENMASK(15, 0)
236266

237-
#define MT_MIB_RVSR1(_band) MT_WF_MIB(_band, 0x724)
267+
#define MT_MIB_RVSR1(_band) MT_WF_MIB(_band, __OFFS(MIB_RVSR1))
238268

239269
/* rx blockack count, 32 bits */
240270
#define MT_MIB_TSCR1(_band) MT_WF_MIB(_band, 0x6b4)
241271

242272
#define MT_MIB_BTSCR0(_band) MT_WF_MIB(_band, 0x5e0)
243-
#define MT_MIB_BTSCR5(_band) MT_WF_MIB(_band, 0x788)
244-
#define MT_MIB_BTSCR6(_band) MT_WF_MIB(_band, 0x798)
273+
#define MT_MIB_BTSCR5(_band) MT_WF_MIB(_band, __OFFS(MIB_BTSCR5))
274+
#define MT_MIB_BTSCR6(_band) MT_WF_MIB(_band, __OFFS(MIB_BTSCR6))
245275

246276
#define MT_MIB_BFTFCR(_band) MT_WF_MIB(_band, 0x5d0)
247277

248-
#define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0xa28 + ((n) << 2))
278+
#define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, __OFFS(MIB_TRDR1) + ((n) << 2))
249279
#define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x0b0 + ((n) << 2))
250280
#define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 4)) & GENMASK(9, 0))
251281

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