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Documentation/devicetree/bindings/clock
include/dt-bindings/power Expand file tree Collapse file tree 3 files changed +42
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lines changed Original file line number Diff line number Diff line change @@ -19,30 +19,48 @@ description: |
1919
2020properties :
2121 compatible :
22- enum :
23- - marvell,pxa1908-apbc
24- - marvell,pxa1908-apbcp
25- - marvell,pxa1908-mpmu
26- - marvell,pxa1908-apmu
22+ oneOf :
23+ - enum :
24+ - marvell,pxa1908-apbc
25+ - marvell,pxa1908-apbcp
26+ - marvell,pxa1908-mpmu
27+ - items :
28+ - const : marvell,pxa1908-apmu
29+ - const : syscon
2730
2831 reg :
2932 maxItems : 1
3033
3134 ' #clock-cells ' :
3235 const : 1
3336
37+ ' #power-domain-cells ' :
38+ const : 1
39+
3440required :
3541 - compatible
3642 - reg
3743 - ' #clock-cells'
3844
3945additionalProperties : false
4046
47+ if :
48+ not :
49+ properties :
50+ compatible :
51+ contains :
52+ const : marvell,pxa1908-apmu
53+
54+ then :
55+ properties :
56+ ' #power-domain-cells ' : false
57+
4158examples :
4259 # APMU block:
4360 - |
4461 clock-controller@d4282800 {
45- compatible = "marvell,pxa1908-apmu";
62+ compatible = "marvell,pxa1908-apmu", "syscon" ;
4663 reg = <0xd4282800 0x400>;
4764 #clock-cells = <1>;
65+ #power-domain-cells = <1>;
4866 };
Original file line number Diff line number Diff line change @@ -2872,6 +2872,7 @@ S: Maintained
28722872F: arch/arm64/boot/dts/marvell/mmp/
28732873F: drivers/clk/mmp/clk-pxa1908*.c
28742874F: include/dt-bindings/clock/marvell,pxa1908.h
2875+ F: include/dt-bindings/power/marvell,pxa1908-power.h
28752876
28762877ARM/Mediatek RTC DRIVER
28772878M: Eddie Huang <eddie.huang@mediatek.com>
Original file line number Diff line number Diff line change 1+ /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2+ /*
3+ * Marvell PXA1908 power domains
4+ *
5+ * Copyright 2025, Duje Mihanović <duje@dujemihanovic.xyz>
6+ */
7+
8+ #ifndef __DTS_MARVELL_PXA1908_POWER_H
9+ #define __DTS_MARVELL_PXA1908_POWER_H
10+
11+ #define PXA1908_POWER_DOMAIN_VPU 0
12+ #define PXA1908_POWER_DOMAIN_GPU 1
13+ #define PXA1908_POWER_DOMAIN_GPU2D 2
14+ #define PXA1908_POWER_DOMAIN_DSI 3
15+ #define PXA1908_POWER_DOMAIN_ISP 4
16+
17+ #endif
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