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crypto: qat - add support for device telemetry
Expose through debugfs device telemetry data for QAT GEN4 devices. This allows to gather metrics about the performance and the utilization of a device. In particular, statistics on (1) the utilization of the PCIe channel, (2) address translation, when SVA is enabled and (3) the internal engines for crypto and data compression. If telemetry is supported by the firmware, the driver allocates a DMA region and a circular buffer. When telemetry is enabled, through the `control` attribute in debugfs, the driver sends to the firmware, via the admin interface, the `TL_START` command. This triggers the device to periodically gather telemetry data from hardware registers and write it into the DMA memory region. The device writes into the shared region every second. The driver, every 500ms, snapshots the DMA shared region into the circular buffer. This is then used to compute basic metric (min/max/average) on each counter, every time the `device_data` attribute is queried. Telemetry counters are exposed through debugfs in the folder /sys/kernel/debug/qat_<device>_<BDF>/telemetry. For details, refer to debugfs-driver-qat_telemetry in Documentation/ABI. This patch is based on earlier work done by Wojciech Ziemba. Signed-off-by: Lucas Segarra Fernandez <lucas.segarra.fernandez@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Damian Muszynski <damian.muszynski@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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‎Documentation/ABI/testing/debugfs-driver-qat_telemetry‎

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What: /sys/kernel/debug/qat_<device>_<BDF>/telemetry/control
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Date: March 2024
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KernelVersion: 6.8
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Contact: qat-linux@intel.com
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Description: (RW) Enables/disables the reporting of telemetry metrics.
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Allowed values to write:
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========================
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* 0: disable telemetry
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* 1: enable telemetry
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* 2, 3, 4: enable telemetry and calculate minimum, maximum
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and average for each counter over 2, 3 or 4 samples
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Returned values:
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================
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* 1-4: telemetry is enabled and running
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* 0: telemetry is disabled
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Example.
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Writing '3' to this file starts the collection of
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telemetry metrics. Samples are collected every second and
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stored in a circular buffer of size 3. These values are then
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used to calculate the minimum, maximum and average for each
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counter. After enabling, counters can be retrieved through
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the ``device_data`` file::
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echo 3 > /sys/kernel/debug/qat_4xxx_0000:6b:00.0/telemetry/control
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Writing '0' to this file stops the collection of telemetry
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metrics::
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echo 0 > /sys/kernel/debug/qat_4xxx_0000:6b:00.0/telemetry/control
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This attribute is only available for qat_4xxx devices.
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What: /sys/kernel/debug/qat_<device>_<BDF>/telemetry/device_data
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Date: March 2024
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KernelVersion: 6.8
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Contact: qat-linux@intel.com
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Description: (RO) Reports device telemetry counters.
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Reads report metrics about performance and utilization of
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a QAT device:
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======================= ========================================
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Field Description
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======================= ========================================
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sample_cnt number of acquisitions of telemetry data
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from the device. Reads are performed
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every 1000 ms.
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pci_trans_cnt number of PCIe partial transactions
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max_rd_lat maximum logged read latency [ns] (could
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be any read operation)
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rd_lat_acc_avg average read latency [ns]
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max_gp_lat max get to put latency [ns] (only takes
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samples for AE0)
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gp_lat_acc_avg average get to put latency [ns]
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bw_in PCIe, write bandwidth [Mbps]
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bw_out PCIe, read bandwidth [Mbps]
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at_page_req_lat_avg Address Translator(AT), average page
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request latency [ns]
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at_trans_lat_avg AT, average page translation latency [ns]
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at_max_tlb_used AT, maximum uTLB used
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util_cpr<N> utilization of Compression slice N [%]
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exec_cpr<N> execution count of Compression slice N
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util_xlt<N> utilization of Translator slice N [%]
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exec_xlt<N> execution count of Translator slice N
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util_dcpr<N> utilization of Decompression slice N [%]
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exec_dcpr<N> execution count of Decompression slice N
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util_pke<N> utilization of PKE N [%]
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exec_pke<N> execution count of PKE N
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util_ucs<N> utilization of UCS slice N [%]
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exec_ucs<N> execution count of UCS slice N
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util_wat<N> utilization of Wireless Authentication
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slice N [%]
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exec_wat<N> execution count of Wireless Authentication
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slice N
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util_wcp<N> utilization of Wireless Cipher slice N [%]
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exec_wcp<N> execution count of Wireless Cipher slice N
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util_cph<N> utilization of Cipher slice N [%]
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exec_cph<N> execution count of Cipher slice N
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util_ath<N> utilization of Authentication slice N [%]
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exec_ath<N> execution count of Authentication slice N
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======================= ========================================
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The telemetry report file can be read with the following command::
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cat /sys/kernel/debug/qat_4xxx_0000:6b:00.0/telemetry/device_data
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If ``control`` is set to 1, only the current values of the
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counters are displayed::
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<counter_name> <current>
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If ``control`` is 2, 3 or 4, counters are displayed in the
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following format::
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<counter_name> <current> <min> <max> <avg>
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If a device lacks of a specific accelerator, the corresponding
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attribute is not reported.
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This attribute is only available for qat_4xxx devices.

‎drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c‎

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@@ -15,6 +15,7 @@
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#include <adf_gen4_pm.h>
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#include <adf_gen4_ras.h>
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#include <adf_gen4_timer.h>
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#include <adf_gen4_tl.h>
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#include "adf_420xx_hw_data.h"
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#include "icp_qat_hw.h"
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@@ -543,6 +544,7 @@ void adf_init_hw_data_420xx(struct adf_hw_device_data *hw_data, u32 dev_id)
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adf_gen4_init_pf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen4_init_dc_ops(&hw_data->dc_ops);
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adf_gen4_init_ras_ops(&hw_data->ras_ops);
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adf_gen4_init_tl_data(&hw_data->tl_data);
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adf_init_rl_data(&hw_data->rl_data);
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}
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‎drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c‎

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#include <adf_gen4_pm.h>
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#include "adf_gen4_ras.h"
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#include <adf_gen4_timer.h>
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#include <adf_gen4_tl.h>
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#include "adf_4xxx_hw_data.h"
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#include "icp_qat_hw.h"
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@@ -453,6 +454,7 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id)
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adf_gen4_init_pf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen4_init_dc_ops(&hw_data->dc_ops);
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adf_gen4_init_ras_ops(&hw_data->ras_ops);
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adf_gen4_init_tl_data(&hw_data->tl_data);
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adf_init_rl_data(&hw_data->rl_data);
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}
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‎drivers/crypto/intel/qat/qat_common/Makefile‎

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@@ -41,9 +41,12 @@ intel_qat-$(CONFIG_DEBUG_FS) += adf_transport_debug.o \
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adf_fw_counters.o \
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adf_cnv_dbgfs.o \
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adf_gen4_pm_debugfs.o \
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adf_gen4_tl.o \
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adf_heartbeat.o \
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adf_heartbeat_dbgfs.o \
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adf_pm_dbgfs.o \
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adf_telemetry.o \
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adf_tl_debugfs.o \
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adf_dbgfs.o
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intel_qat-$(CONFIG_PCI_IOV) += adf_sriov.o adf_vf_isr.o adf_pfvf_utils.o \

‎drivers/crypto/intel/qat/qat_common/adf_accel_devices.h‎

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#include <linux/types.h>
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#include "adf_cfg_common.h"
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#include "adf_rl.h"
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#include "adf_telemetry.h"
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#include "adf_pfvf_msg.h"
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#define ADF_DH895XCC_DEVICE_NAME "dh895xcc"
@@ -254,6 +255,7 @@ struct adf_hw_device_data {
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struct adf_ras_ops ras_ops;
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struct adf_dev_err_mask dev_err_mask;
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struct adf_rl_hw_data rl_data;
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struct adf_tl_hw_data tl_data;
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const char *fw_name;
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const char *fw_mmp_name;
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u32 fuses;
@@ -308,6 +310,7 @@ struct adf_hw_device_data {
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#define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_ops)
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#define GET_PFVF_OPS(accel_dev) (&(accel_dev)->hw_device->pfvf_ops)
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#define GET_DC_OPS(accel_dev) (&(accel_dev)->hw_device->dc_ops)
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#define GET_TL_DATA(accel_dev) GET_HW_DATA(accel_dev)->tl_data
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#define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev
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struct adf_admin_comms;
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struct adf_cfg_device_data *cfg;
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struct adf_fw_loader_data *fw_loader;
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struct adf_admin_comms *admin;
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struct adf_telemetry *telemetry;
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struct adf_dc_data *dc_data;
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struct adf_pm power_management;
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struct list_head crypto_list;

‎drivers/crypto/intel/qat/qat_common/adf_dbgfs.c‎

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#include "adf_fw_counters.h"
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#include "adf_heartbeat_dbgfs.h"
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#include "adf_pm_dbgfs.h"
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#include "adf_tl_debugfs.h"
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/**
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* adf_dbgfs_init() - add persistent debugfs entries
@@ -66,6 +67,7 @@ void adf_dbgfs_add(struct adf_accel_dev *accel_dev)
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adf_heartbeat_dbgfs_add(accel_dev);
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adf_pm_dbgfs_add(accel_dev);
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adf_cnv_dbgfs_add(accel_dev);
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adf_tl_dbgfs_add(accel_dev);
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}
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}
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@@ -79,6 +81,7 @@ void adf_dbgfs_rm(struct adf_accel_dev *accel_dev)
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return;
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8183
if (!accel_dev->is_vf) {
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adf_tl_dbgfs_rm(accel_dev);
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adf_cnv_dbgfs_rm(accel_dev);
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adf_pm_dbgfs_rm(accel_dev);
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adf_heartbeat_dbgfs_rm(accel_dev);

‎drivers/crypto/intel/qat/qat_common/adf_gen4_tl.c‎

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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2023 Intel Corporation. */
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include "adf_gen4_tl.h"
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#include "adf_telemetry.h"
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#include "adf_tl_debugfs.h"
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#define ADF_GEN4_TL_DEV_REG_OFF(reg) ADF_TL_DEV_REG_OFF(reg, gen4)
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#define ADF_GEN4_TL_SL_UTIL_COUNTER(_name) \
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ADF_TL_COUNTER("util_" #_name, \
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ADF_TL_SIMPLE_COUNT, \
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ADF_TL_SLICE_REG_OFF(_name, reg_tm_slice_util, gen4))
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#define ADF_GEN4_TL_SL_EXEC_COUNTER(_name) \
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ADF_TL_COUNTER("exec_" #_name, \
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ADF_TL_SIMPLE_COUNT, \
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ADF_TL_SLICE_REG_OFF(_name, reg_tm_slice_exec_cnt, gen4))
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/* Device level counters. */
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static const struct adf_tl_dbg_counter dev_counters[] = {
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/* PCIe partial transactions. */
25+
ADF_TL_COUNTER(PCI_TRANS_CNT_NAME, ADF_TL_SIMPLE_COUNT,
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_pci_trans_cnt)),
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/* Max read latency[ns]. */
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ADF_TL_COUNTER(MAX_RD_LAT_NAME, ADF_TL_COUNTER_NS,
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_rd_lat_max)),
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/* Read latency average[ns]. */
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ADF_TL_COUNTER_LATENCY(RD_LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_rd_lat_acc),
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_rd_cmpl_cnt)),
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/* Max get to put latency[ns]. */
35+
ADF_TL_COUNTER(MAX_LAT_NAME, ADF_TL_COUNTER_NS,
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_gp_lat_max)),
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/* Get to put latency average[ns]. */
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ADF_TL_COUNTER_LATENCY(LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,
39+
ADF_GEN4_TL_DEV_REG_OFF(reg_tl_gp_lat_acc),
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_ae_put_cnt)),
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/* PCIe write bandwidth[Mbps]. */
42+
ADF_TL_COUNTER(BW_IN_NAME, ADF_TL_COUNTER_MBPS,
43+
ADF_GEN4_TL_DEV_REG_OFF(reg_tl_bw_in)),
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/* PCIe read bandwidth[Mbps]. */
45+
ADF_TL_COUNTER(BW_OUT_NAME, ADF_TL_COUNTER_MBPS,
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ADF_GEN4_TL_DEV_REG_OFF(reg_tl_bw_out)),
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/* Page request latency average[ns]. */
48+
ADF_TL_COUNTER_LATENCY(PAGE_REQ_LAT_NAME, ADF_TL_COUNTER_NS_AVG,
49+
ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_page_req_lat_acc),
50+
ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_page_req_cnt)),
51+
/* Page translation latency average[ns]. */
52+
ADF_TL_COUNTER_LATENCY(AT_TRANS_LAT_NAME, ADF_TL_COUNTER_NS_AVG,
53+
ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_trans_lat_acc),
54+
ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_trans_lat_cnt)),
55+
/* Maximum uTLB used. */
56+
ADF_TL_COUNTER(AT_MAX_UTLB_USED_NAME, ADF_TL_SIMPLE_COUNT,
57+
ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_max_tlb_used)),
58+
};
59+
60+
/* Slice utilization counters. */
61+
static const struct adf_tl_dbg_counter sl_util_counters[ADF_TL_SL_CNT_COUNT] = {
62+
/* Compression slice utilization. */
63+
ADF_GEN4_TL_SL_UTIL_COUNTER(cpr),
64+
/* Translator slice utilization. */
65+
ADF_GEN4_TL_SL_UTIL_COUNTER(xlt),
66+
/* Decompression slice utilization. */
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ADF_GEN4_TL_SL_UTIL_COUNTER(dcpr),
68+
/* PKE utilization. */
69+
ADF_GEN4_TL_SL_UTIL_COUNTER(pke),
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/* Wireless Authentication slice utilization. */
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ADF_GEN4_TL_SL_UTIL_COUNTER(wat),
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/* Wireless Cipher slice utilization. */
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ADF_GEN4_TL_SL_UTIL_COUNTER(wcp),
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/* UCS slice utilization. */
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ADF_GEN4_TL_SL_UTIL_COUNTER(ucs),
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/* Cipher slice utilization. */
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ADF_GEN4_TL_SL_UTIL_COUNTER(cph),
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/* Authentication slice utilization. */
79+
ADF_GEN4_TL_SL_UTIL_COUNTER(ath),
80+
};
81+
82+
/* Slice execution counters. */
83+
static const struct adf_tl_dbg_counter sl_exec_counters[ADF_TL_SL_CNT_COUNT] = {
84+
/* Compression slice execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(cpr),
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/* Translator slice execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(xlt),
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/* Decompression slice execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(dcpr),
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/* PKE execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(pke),
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/* Wireless Authentication slice execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(wat),
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/* Wireless Cipher slice execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(wcp),
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/* UCS slice execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(ucs),
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/* Cipher slice execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(cph),
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/* Authentication slice execution count. */
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ADF_GEN4_TL_SL_EXEC_COUNTER(ath),
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};
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104+
void adf_gen4_init_tl_data(struct adf_tl_hw_data *tl_data)
105+
{
106+
tl_data->layout_sz = ADF_GEN4_TL_LAYOUT_SZ;
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tl_data->slice_reg_sz = ADF_GEN4_TL_SLICE_REG_SZ;
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tl_data->num_hbuff = ADF_GEN4_TL_NUM_HIST_BUFFS;
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tl_data->msg_cnt_off = ADF_GEN4_TL_MSG_CNT_OFF;
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tl_data->cpp_ns_per_cycle = ADF_GEN4_CPP_NS_PER_CYCLE;
111+
tl_data->bw_units_to_bytes = ADF_GEN4_TL_BW_HW_UNITS_TO_BYTES;
112+
113+
tl_data->dev_counters = dev_counters;
114+
tl_data->num_dev_counters = ARRAY_SIZE(dev_counters);
115+
tl_data->sl_util_counters = sl_util_counters;
116+
tl_data->sl_exec_counters = sl_exec_counters;
117+
}
118+
EXPORT_SYMBOL_GPL(adf_gen4_init_tl_data);

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