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Ronak DoshiPaolo Abeni
Ronak Doshi
authored and
Paolo Abeni
committed
vmxnet3: add support for capability registers
This patch enhances vmxnet3 to suuport capability registers which allows it to enable features selectively. The DCR register tracks the capabilities vmxnet3 device supports. The PTCR register states the capabilities that the passthrough device supports. With the help of these registers, vmxnet3 can enable only those features which the passthrough device supoprts. This allows smooth trasition to Uniform-Passthrough (UPT) mode if the virtual nic requests it. If PTCR register returns nothing or error it means UPT is not being requested and vnic will continue in emulation mode. Signed-off-by: Ronak Doshi <doshir@vmware.com> Acked-by: Guolin Yang <gyang@vmware.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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‎drivers/net/vmxnet3/vmxnet3_defs.h‎

Lines changed: 36 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,13 @@ enum {
4040
VMXNET3_REG_MACL = 0x28, /* MAC Address Low */
4141
VMXNET3_REG_MACH = 0x30, /* MAC Address High */
4242
VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */
43-
VMXNET3_REG_ECR = 0x40 /* Event Cause Register */
43+
VMXNET3_REG_ECR = 0x40, /* Event Cause Register */
44+
VMXNET3_REG_DCR = 0x48, /* Device capability register,
45+
* from 0x48 to 0x80
46+
*/
47+
VMXNET3_REG_PTCR = 0x88, /* Passthru capbility register
48+
* from 0x88 to 0xb0
49+
*/
4450
};
4551

4652
/* BAR 0 */
@@ -101,6 +107,9 @@ enum {
101107
VMXNET3_CMD_GET_RESERVED2,
102108
VMXNET3_CMD_GET_RESERVED3,
103109
VMXNET3_CMD_GET_MAX_QUEUES_CONF,
110+
VMXNET3_CMD_GET_RESERVED4,
111+
VMXNET3_CMD_GET_MAX_CAPABILITIES,
112+
VMXNET3_CMD_GET_DCR0_REG,
104113
};
105114

106115
/*
@@ -801,4 +810,30 @@ struct Vmxnet3_DriverShared {
801810
#define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */
802811
#define VMXNET3_LINK_DOWN 0
803812

813+
#define VMXNET3_DCR_ERROR 31 /* error when bit 31 of DCR is set */
814+
#define VMXNET3_CAP_UDP_RSS 0 /* bit 0 of DCR 0 */
815+
#define VMXNET3_CAP_ESP_RSS_IPV4 1 /* bit 1 of DCR 0 */
816+
#define VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD 2 /* bit 2 of DCR 0 */
817+
#define VMXNET3_CAP_GENEVE_TSO 3 /* bit 3 of DCR 0 */
818+
#define VMXNET3_CAP_VXLAN_CHECKSUM_OFFLOAD 4 /* bit 4 of DCR 0 */
819+
#define VMXNET3_CAP_VXLAN_TSO 5 /* bit 5 of DCR 0 */
820+
#define VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD 6 /* bit 6 of DCR 0 */
821+
#define VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD 7 /* bit 7 of DCR 0 */
822+
#define VMXNET3_CAP_PKT_STEERING_IPV4 8 /* bit 8 of DCR 0 */
823+
#define VMXNET3_CAP_VERSION_4_MAX VMXNET3_CAP_PKT_STEERING_IPV4
824+
#define VMXNET3_CAP_ESP_RSS_IPV6 9 /* bit 9 of DCR 0 */
825+
#define VMXNET3_CAP_VERSION_5_MAX VMXNET3_CAP_ESP_RSS_IPV6
826+
#define VMXNET3_CAP_ESP_OVER_UDP_RSS 10 /* bit 10 of DCR 0 */
827+
#define VMXNET3_CAP_INNER_RSS 11 /* bit 11 of DCR 0 */
828+
#define VMXNET3_CAP_INNER_ESP_RSS 12 /* bit 12 of DCR 0 */
829+
#define VMXNET3_CAP_CRC32_HASH_FUNC 13 /* bit 13 of DCR 0 */
830+
#define VMXNET3_CAP_VERSION_6_MAX VMXNET3_CAP_CRC32_HASH_FUNC
831+
#define VMXNET3_CAP_OAM_FILTER 14 /* bit 14 of DCR 0 */
832+
#define VMXNET3_CAP_ESP_QS 15 /* bit 15 of DCR 0 */
833+
#define VMXNET3_CAP_LARGE_BAR 16 /* bit 16 of DCR 0 */
834+
#define VMXNET3_CAP_OOORX_COMP 17 /* bit 17 of DCR 0 */
835+
#define VMXNET3_CAP_VERSION_7_MAX 18
836+
/* when new capability is introduced, update VMXNET3_CAP_MAX */
837+
#define VMXNET3_CAP_MAX VMXNET3_CAP_VERSION_7_MAX
838+
804839
#endif /* _VMXNET3_DEFS_H_ */

‎drivers/net/vmxnet3/vmxnet3_drv.c‎

Lines changed: 97 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -130,6 +130,20 @@ vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
130130
netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
131131
}
132132

133+
/* Check if capability is supported by UPT device or
134+
* UPT is even requested
135+
*/
136+
bool
137+
vmxnet3_check_ptcapability(u32 cap_supported, u32 cap)
138+
{
139+
if (cap_supported & (1UL << VMXNET3_DCR_ERROR) ||
140+
cap_supported & (1UL << cap)) {
141+
return true;
142+
}
143+
144+
return false;
145+
}
146+
133147

134148
/*
135149
* Check the link state. This may start or stop the tx queue.
@@ -2671,6 +2685,36 @@ vmxnet3_init_rssfields(struct vmxnet3_adapter *adapter)
26712685
adapter->rss_fields =
26722686
VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
26732687
} else {
2688+
if (VMXNET3_VERSION_GE_7(adapter)) {
2689+
if ((adapter->rss_fields & VMXNET3_RSS_FIELDS_UDPIP4 ||
2690+
adapter->rss_fields & VMXNET3_RSS_FIELDS_UDPIP6) &&
2691+
vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
2692+
VMXNET3_CAP_UDP_RSS)) {
2693+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_UDP_RSS;
2694+
} else {
2695+
adapter->dev_caps[0] &= ~(1UL << VMXNET3_CAP_UDP_RSS);
2696+
}
2697+
2698+
if ((adapter->rss_fields & VMXNET3_RSS_FIELDS_ESPIP4) &&
2699+
vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
2700+
VMXNET3_CAP_ESP_RSS_IPV4)) {
2701+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_ESP_RSS_IPV4;
2702+
} else {
2703+
adapter->dev_caps[0] &= ~(1UL << VMXNET3_CAP_ESP_RSS_IPV4);
2704+
}
2705+
2706+
if ((adapter->rss_fields & VMXNET3_RSS_FIELDS_ESPIP6) &&
2707+
vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
2708+
VMXNET3_CAP_ESP_RSS_IPV6)) {
2709+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_ESP_RSS_IPV6;
2710+
} else {
2711+
adapter->dev_caps[0] &= ~(1UL << VMXNET3_CAP_ESP_RSS_IPV6);
2712+
}
2713+
2714+
VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DCR, adapter->dev_caps[0]);
2715+
VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_DCR0_REG);
2716+
adapter->dev_caps[0] = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2717+
}
26742718
cmdInfo->setRssFields = adapter->rss_fields;
26752719
VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
26762720
VMXNET3_CMD_SET_RSS_FIELDS);
@@ -3185,6 +3229,47 @@ vmxnet3_declare_features(struct vmxnet3_adapter *adapter)
31853229
NETIF_F_GSO_UDP_TUNNEL_CSUM;
31863230
}
31873231

3232+
if (VMXNET3_VERSION_GE_7(adapter)) {
3233+
unsigned long flags;
3234+
3235+
if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
3236+
VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD)) {
3237+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD;
3238+
}
3239+
if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
3240+
VMXNET3_CAP_VXLAN_CHECKSUM_OFFLOAD)) {
3241+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_VXLAN_CHECKSUM_OFFLOAD;
3242+
}
3243+
if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
3244+
VMXNET3_CAP_GENEVE_TSO)) {
3245+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_GENEVE_TSO;
3246+
}
3247+
if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
3248+
VMXNET3_CAP_VXLAN_TSO)) {
3249+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_VXLAN_TSO;
3250+
}
3251+
if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
3252+
VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD)) {
3253+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD;
3254+
}
3255+
if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
3256+
VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD)) {
3257+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD;
3258+
}
3259+
3260+
VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DCR, adapter->dev_caps[0]);
3261+
spin_lock_irqsave(&adapter->cmd_lock, flags);
3262+
VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_DCR0_REG);
3263+
adapter->dev_caps[0] = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
3264+
spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3265+
3266+
if (!(adapter->dev_caps[0] & (1UL << VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD)) &&
3267+
!(adapter->dev_caps[0] & (1UL << VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD))) {
3268+
netdev->hw_enc_features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
3269+
netdev->features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
3270+
}
3271+
}
3272+
31883273
netdev->vlan_features = netdev->hw_features &
31893274
~(NETIF_F_HW_VLAN_CTAG_TX |
31903275
NETIF_F_HW_VLAN_CTAG_RX);
@@ -3520,6 +3605,18 @@ vmxnet3_probe_device(struct pci_dev *pdev,
35203605
goto err_ver;
35213606
}
35223607

3608+
if (VMXNET3_VERSION_GE_7(adapter)) {
3609+
adapter->devcap_supported[0] = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_DCR);
3610+
adapter->ptcap_supported[0] = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_PTCR);
3611+
if (adapter->dev_caps[0])
3612+
VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DCR, adapter->dev_caps[0]);
3613+
3614+
spin_lock_irqsave(&adapter->cmd_lock, flags);
3615+
VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_DCR0_REG);
3616+
adapter->dev_caps[0] = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
3617+
spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3618+
}
3619+
35233620
if (VMXNET3_VERSION_GE_6(adapter)) {
35243621
spin_lock_irqsave(&adapter->cmd_lock, flags);
35253622
VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,

‎drivers/net/vmxnet3/vmxnet3_ethtool.c‎

Lines changed: 96 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -298,16 +298,58 @@ netdev_features_t vmxnet3_features_check(struct sk_buff *skb,
298298
return features;
299299
}
300300

301-
static void vmxnet3_enable_encap_offloads(struct net_device *netdev)
301+
static void vmxnet3_enable_encap_offloads(struct net_device *netdev, netdev_features_t features)
302302
{
303303
struct vmxnet3_adapter *adapter = netdev_priv(netdev);
304304

305305
if (VMXNET3_VERSION_GE_4(adapter)) {
306306
netdev->hw_enc_features |= NETIF_F_SG | NETIF_F_RXCSUM |
307307
NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
308308
NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
309-
NETIF_F_LRO | NETIF_F_GSO_UDP_TUNNEL |
310-
NETIF_F_GSO_UDP_TUNNEL_CSUM;
309+
NETIF_F_LRO;
310+
if (features & NETIF_F_GSO_UDP_TUNNEL)
311+
netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
312+
if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM)
313+
netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
314+
}
315+
if (VMXNET3_VERSION_GE_7(adapter)) {
316+
unsigned long flags;
317+
318+
if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
319+
VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD)) {
320+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD;
321+
}
322+
if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
323+
VMXNET3_CAP_VXLAN_CHECKSUM_OFFLOAD)) {
324+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_VXLAN_CHECKSUM_OFFLOAD;
325+
}
326+
if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
327+
VMXNET3_CAP_GENEVE_TSO)) {
328+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_GENEVE_TSO;
329+
}
330+
if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
331+
VMXNET3_CAP_VXLAN_TSO)) {
332+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_VXLAN_TSO;
333+
}
334+
if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
335+
VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD)) {
336+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD;
337+
}
338+
if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
339+
VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD)) {
340+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD;
341+
}
342+
343+
VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DCR, adapter->dev_caps[0]);
344+
spin_lock_irqsave(&adapter->cmd_lock, flags);
345+
VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_DCR0_REG);
346+
adapter->dev_caps[0] = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
347+
spin_unlock_irqrestore(&adapter->cmd_lock, flags);
348+
349+
if (!(adapter->dev_caps[0] & (1UL << VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD)) &&
350+
!(adapter->dev_caps[0] & (1UL << VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD))) {
351+
netdev->hw_enc_features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
352+
}
311353
}
312354
}
313355

@@ -322,6 +364,22 @@ static void vmxnet3_disable_encap_offloads(struct net_device *netdev)
322364
NETIF_F_LRO | NETIF_F_GSO_UDP_TUNNEL |
323365
NETIF_F_GSO_UDP_TUNNEL_CSUM);
324366
}
367+
if (VMXNET3_VERSION_GE_7(adapter)) {
368+
unsigned long flags;
369+
370+
adapter->dev_caps[0] &= ~(1UL << VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD |
371+
1UL << VMXNET3_CAP_VXLAN_CHECKSUM_OFFLOAD |
372+
1UL << VMXNET3_CAP_GENEVE_TSO |
373+
1UL << VMXNET3_CAP_VXLAN_TSO |
374+
1UL << VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD |
375+
1UL << VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD);
376+
377+
VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DCR, adapter->dev_caps[0]);
378+
spin_lock_irqsave(&adapter->cmd_lock, flags);
379+
VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_DCR0_REG);
380+
adapter->dev_caps[0] = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
381+
spin_unlock_irqrestore(&adapter->cmd_lock, flags);
382+
}
325383
}
326384

327385
int vmxnet3_set_features(struct net_device *netdev, netdev_features_t features)
@@ -357,8 +415,8 @@ int vmxnet3_set_features(struct net_device *netdev, netdev_features_t features)
357415
adapter->shared->devRead.misc.uptFeatures &=
358416
~UPT1_F_RXVLAN;
359417

360-
if ((features & tun_offload_mask) != 0 && !udp_tun_enabled) {
361-
vmxnet3_enable_encap_offloads(netdev);
418+
if ((features & tun_offload_mask) != 0) {
419+
vmxnet3_enable_encap_offloads(netdev, features);
362420
adapter->shared->devRead.misc.uptFeatures |=
363421
UPT1_F_RXINNEROFLD;
364422
} else if ((features & tun_offload_mask) == 0 &&
@@ -913,6 +971,39 @@ vmxnet3_set_rss_hash_opt(struct net_device *netdev,
913971
union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
914972
unsigned long flags;
915973

974+
if (VMXNET3_VERSION_GE_7(adapter)) {
975+
if ((rss_fields & VMXNET3_RSS_FIELDS_UDPIP4 ||
976+
rss_fields & VMXNET3_RSS_FIELDS_UDPIP6) &&
977+
vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
978+
VMXNET3_CAP_UDP_RSS)) {
979+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_UDP_RSS;
980+
} else {
981+
adapter->dev_caps[0] &= ~(1UL << VMXNET3_CAP_UDP_RSS);
982+
}
983+
if ((rss_fields & VMXNET3_RSS_FIELDS_ESPIP4) &&
984+
vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
985+
VMXNET3_CAP_ESP_RSS_IPV4)) {
986+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_ESP_RSS_IPV4;
987+
} else {
988+
adapter->dev_caps[0] &= ~(1UL << VMXNET3_CAP_ESP_RSS_IPV4);
989+
}
990+
if ((rss_fields & VMXNET3_RSS_FIELDS_ESPIP6) &&
991+
vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
992+
VMXNET3_CAP_ESP_RSS_IPV6)) {
993+
adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_ESP_RSS_IPV6;
994+
} else {
995+
adapter->dev_caps[0] &= ~(1UL << VMXNET3_CAP_ESP_RSS_IPV6);
996+
}
997+
998+
VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DCR,
999+
adapter->dev_caps[0]);
1000+
spin_lock_irqsave(&adapter->cmd_lock, flags);
1001+
VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1002+
VMXNET3_CMD_GET_DCR0_REG);
1003+
adapter->dev_caps[0] = VMXNET3_READ_BAR1_REG(adapter,
1004+
VMXNET3_REG_CMD);
1005+
spin_unlock_irqrestore(&adapter->cmd_lock, flags);
1006+
}
9161007
spin_lock_irqsave(&adapter->cmd_lock, flags);
9171008
cmdInfo->setRssFields = rss_fields;
9181009
VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,

‎drivers/net/vmxnet3/vmxnet3_int.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -403,6 +403,9 @@ struct vmxnet3_adapter {
403403
dma_addr_t pm_conf_pa;
404404
dma_addr_t rss_conf_pa;
405405
bool queuesExtEnabled;
406+
u32 devcap_supported[8];
407+
u32 ptcap_supported[8];
408+
u32 dev_caps[8];
406409
};
407410

408411
#define VMXNET3_WRITE_BAR0_REG(adapter, reg, val) \
@@ -497,6 +500,7 @@ void vmxnet3_set_ethtool_ops(struct net_device *netdev);
497500

498501
void vmxnet3_get_stats64(struct net_device *dev,
499502
struct rtnl_link_stats64 *stats);
503+
bool vmxnet3_check_ptcapability(u32 cap_supported, u32 cap);
500504

501505
extern char vmxnet3_driver_name[];
502506
#endif

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