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drm/i915/irq: s/gen3/gen2/
Now that we use the gen3 codepaths also for gen2 rename everything to gen2_ to match. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241008214349.23331-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
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5 files changed

+62
-62
lines changed

5 files changed

+62
-62
lines changed

‎drivers/gpu/drm/i915/display/intel_display_irq.c‎

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -1496,7 +1496,7 @@ void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
14961496

14971497
i9xx_pipestat_irq_reset(dev_priv);
14981498

1499-
gen3_irq_reset(uncore, VLV_IRQ_REGS);
1499+
gen2_irq_reset(uncore, VLV_IRQ_REGS);
15001500
dev_priv->irq_mask = ~0u;
15011501
}
15021502

@@ -1539,7 +1539,7 @@ void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
15391539

15401540
dev_priv->irq_mask = ~enable_mask;
15411541

1542-
gen3_irq_init(uncore, VLV_IRQ_REGS, dev_priv->irq_mask, enable_mask);
1542+
gen2_irq_init(uncore, VLV_IRQ_REGS, dev_priv->irq_mask, enable_mask);
15431543
}
15441544

15451545
void gen8_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -1556,10 +1556,10 @@ void gen8_display_irq_reset(struct drm_i915_private *dev_priv)
15561556
for_each_pipe(dev_priv, pipe)
15571557
if (intel_display_power_is_enabled(dev_priv,
15581558
POWER_DOMAIN_PIPE(pipe)))
1559-
gen3_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe));
1559+
gen2_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe));
15601560

1561-
gen3_irq_reset(uncore, GEN8_DE_PORT_IRQ_REGS);
1562-
gen3_irq_reset(uncore, GEN8_DE_MISC_IRQ_REGS);
1561+
gen2_irq_reset(uncore, GEN8_DE_PORT_IRQ_REGS);
1562+
gen2_irq_reset(uncore, GEN8_DE_MISC_IRQ_REGS);
15631563
}
15641564

15651565
void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -1599,18 +1599,18 @@ void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
15991599
for_each_pipe(dev_priv, pipe)
16001600
if (intel_display_power_is_enabled(dev_priv,
16011601
POWER_DOMAIN_PIPE(pipe)))
1602-
gen3_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe));
1602+
gen2_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe));
16031603

1604-
gen3_irq_reset(uncore, GEN8_DE_PORT_IRQ_REGS);
1605-
gen3_irq_reset(uncore, GEN8_DE_MISC_IRQ_REGS);
1604+
gen2_irq_reset(uncore, GEN8_DE_PORT_IRQ_REGS);
1605+
gen2_irq_reset(uncore, GEN8_DE_MISC_IRQ_REGS);
16061606

16071607
if (DISPLAY_VER(dev_priv) >= 14)
1608-
gen3_irq_reset(uncore, PICAINTERRUPT_IRQ_REGS);
1608+
gen2_irq_reset(uncore, PICAINTERRUPT_IRQ_REGS);
16091609
else
1610-
gen3_irq_reset(uncore, GEN11_DE_HPD_IRQ_REGS);
1610+
gen2_irq_reset(uncore, GEN11_DE_HPD_IRQ_REGS);
16111611

16121612
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
1613-
gen3_irq_reset(uncore, SDE_IRQ_REGS);
1613+
gen2_irq_reset(uncore, SDE_IRQ_REGS);
16141614
}
16151615

16161616
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -1630,7 +1630,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
16301630
}
16311631

16321632
for_each_pipe_masked(dev_priv, pipe, pipe_mask)
1633-
gen3_irq_init(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe),
1633+
gen2_irq_init(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe),
16341634
dev_priv->display.irq.de_irq_mask[pipe],
16351635
~dev_priv->display.irq.de_irq_mask[pipe] | extra_ier);
16361636

@@ -1651,7 +1651,7 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
16511651
}
16521652

16531653
for_each_pipe_masked(dev_priv, pipe, pipe_mask)
1654-
gen3_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe));
1654+
gen2_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe));
16551655

16561656
spin_unlock_irq(&dev_priv->irq_lock);
16571657

@@ -1685,7 +1685,7 @@ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
16851685
else
16861686
mask = SDE_GMBUS_CPT;
16871687

1688-
gen3_irq_init(uncore, SDE_IRQ_REGS, ~mask, 0xffffffff);
1688+
gen2_irq_init(uncore, SDE_IRQ_REGS, ~mask, 0xffffffff);
16891689
}
16901690

16911691
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
@@ -1742,7 +1742,7 @@ void ilk_de_irq_postinstall(struct drm_i915_private *i915)
17421742
}
17431743

17441744
if (IS_HASWELL(i915)) {
1745-
gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
1745+
gen2_assert_iir_is_zero(uncore, EDP_PSR_IIR);
17461746
display_mask |= DE_EDP_PSR_INT_HSW;
17471747
}
17481748

@@ -1753,7 +1753,7 @@ void ilk_de_irq_postinstall(struct drm_i915_private *i915)
17531753

17541754
ibx_irq_postinstall(i915);
17551755

1756-
gen3_irq_init(uncore, DE_IRQ_REGS, i915->irq_mask,
1756+
gen2_irq_init(uncore, DE_IRQ_REGS, i915->irq_mask,
17571757
display_mask | extra_mask);
17581758
}
17591759

@@ -1827,32 +1827,32 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
18271827
if (!intel_display_power_is_enabled(dev_priv, domain))
18281828
continue;
18291829

1830-
gen3_assert_iir_is_zero(uncore,
1830+
gen2_assert_iir_is_zero(uncore,
18311831
TRANS_PSR_IIR(dev_priv, trans));
18321832
}
18331833
} else {
1834-
gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
1834+
gen2_assert_iir_is_zero(uncore, EDP_PSR_IIR);
18351835
}
18361836

18371837
for_each_pipe(dev_priv, pipe) {
18381838
dev_priv->display.irq.de_irq_mask[pipe] = ~de_pipe_masked;
18391839

18401840
if (intel_display_power_is_enabled(dev_priv,
18411841
POWER_DOMAIN_PIPE(pipe)))
1842-
gen3_irq_init(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe),
1842+
gen2_irq_init(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe),
18431843
dev_priv->display.irq.de_irq_mask[pipe],
18441844
de_pipe_enables);
18451845
}
18461846

1847-
gen3_irq_init(uncore, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, de_port_enables);
1848-
gen3_irq_init(uncore, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, de_misc_masked);
1847+
gen2_irq_init(uncore, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, de_port_enables);
1848+
gen2_irq_init(uncore, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, de_misc_masked);
18491849

18501850
if (IS_DISPLAY_VER(dev_priv, 11, 13)) {
18511851
u32 de_hpd_masked = 0;
18521852
u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
18531853
GEN11_DE_TBT_HOTPLUG_MASK;
18541854

1855-
gen3_irq_init(uncore, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked,
1855+
gen2_irq_init(uncore, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked,
18561856
de_hpd_enables);
18571857
}
18581858
}
@@ -1865,18 +1865,18 @@ static void mtp_irq_postinstall(struct drm_i915_private *i915)
18651865
u32 de_hpd_enables = de_hpd_mask | XELPDP_DP_ALT_HOTPLUG_MASK |
18661866
XELPDP_TBT_HOTPLUG_MASK;
18671867

1868-
gen3_irq_init(uncore, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask,
1868+
gen2_irq_init(uncore, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask,
18691869
de_hpd_enables);
18701870

1871-
gen3_irq_init(uncore, SDE_IRQ_REGS, ~sde_mask, 0xffffffff);
1871+
gen2_irq_init(uncore, SDE_IRQ_REGS, ~sde_mask, 0xffffffff);
18721872
}
18731873

18741874
static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
18751875
{
18761876
struct intel_uncore *uncore = &dev_priv->uncore;
18771877
u32 mask = SDE_GMBUS_ICP;
18781878

1879-
gen3_irq_init(uncore, SDE_IRQ_REGS, ~mask, 0xffffffff);
1879+
gen2_irq_init(uncore, SDE_IRQ_REGS, ~mask, 0xffffffff);
18801880
}
18811881

18821882
void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv)

‎drivers/gpu/drm/i915/gt/intel_gt_irq.c‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -452,10 +452,10 @@ void gen8_gt_irq_reset(struct intel_gt *gt)
452452
{
453453
struct intel_uncore *uncore = gt->uncore;
454454

455-
gen3_irq_reset(uncore, GEN8_GT_IRQ_REGS(0));
456-
gen3_irq_reset(uncore, GEN8_GT_IRQ_REGS(1));
457-
gen3_irq_reset(uncore, GEN8_GT_IRQ_REGS(2));
458-
gen3_irq_reset(uncore, GEN8_GT_IRQ_REGS(3));
455+
gen2_irq_reset(uncore, GEN8_GT_IRQ_REGS(0));
456+
gen2_irq_reset(uncore, GEN8_GT_IRQ_REGS(1));
457+
gen2_irq_reset(uncore, GEN8_GT_IRQ_REGS(2));
458+
gen2_irq_reset(uncore, GEN8_GT_IRQ_REGS(3));
459459
}
460460

461461
void gen8_gt_irq_postinstall(struct intel_gt *gt)
@@ -476,14 +476,14 @@ void gen8_gt_irq_postinstall(struct intel_gt *gt)
476476

477477
gt->pm_ier = 0x0;
478478
gt->pm_imr = ~gt->pm_ier;
479-
gen3_irq_init(uncore, GEN8_GT_IRQ_REGS(0), ~gt_interrupts[0], gt_interrupts[0]);
480-
gen3_irq_init(uncore, GEN8_GT_IRQ_REGS(1), ~gt_interrupts[1], gt_interrupts[1]);
479+
gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(0), ~gt_interrupts[0], gt_interrupts[0]);
480+
gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(1), ~gt_interrupts[1], gt_interrupts[1]);
481481
/*
482482
* RPS interrupts will get enabled/disabled on demand when RPS itself
483483
* is enabled/disabled. Same wil be the case for GuC interrupts.
484484
*/
485-
gen3_irq_init(uncore, GEN8_GT_IRQ_REGS(2), gt->pm_imr, gt->pm_ier);
486-
gen3_irq_init(uncore, GEN8_GT_IRQ_REGS(3), ~gt_interrupts[3], gt_interrupts[3]);
485+
gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(2), gt->pm_imr, gt->pm_ier);
486+
gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(3), ~gt_interrupts[3], gt_interrupts[3]);
487487
}
488488

489489
static void gen5_gt_update_irq(struct intel_gt *gt,
@@ -514,9 +514,9 @@ void gen5_gt_irq_reset(struct intel_gt *gt)
514514
{
515515
struct intel_uncore *uncore = gt->uncore;
516516

517-
gen3_irq_reset(uncore, GT_IRQ_REGS);
517+
gen2_irq_reset(uncore, GT_IRQ_REGS);
518518
if (GRAPHICS_VER(gt->i915) >= 6)
519-
gen3_irq_reset(uncore, GEN6_PM_IRQ_REGS);
519+
gen2_irq_reset(uncore, GEN6_PM_IRQ_REGS);
520520
}
521521

522522
void gen5_gt_irq_postinstall(struct intel_gt *gt)
@@ -538,7 +538,7 @@ void gen5_gt_irq_postinstall(struct intel_gt *gt)
538538
else
539539
gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
540540

541-
gen3_irq_init(uncore, GT_IRQ_REGS, gt->gt_imr, gt_irqs);
541+
gen2_irq_init(uncore, GT_IRQ_REGS, gt->gt_imr, gt_irqs);
542542

543543
if (GRAPHICS_VER(gt->i915) >= 6) {
544544
/*
@@ -551,6 +551,6 @@ void gen5_gt_irq_postinstall(struct intel_gt *gt)
551551
}
552552

553553
gt->pm_imr = 0xffffffff;
554-
gen3_irq_init(uncore, GEN6_PM_IRQ_REGS, gt->pm_imr, pm_irqs);
554+
gen2_irq_init(uncore, GEN6_PM_IRQ_REGS, gt->pm_imr, pm_irqs);
555555
}
556556
}

‎drivers/gpu/drm/i915/i915_irq.c‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ static inline void pmu_irq_stats(struct drm_i915_private *i915,
7777
WRITE_ONCE(i915->pmu.irq_count, i915->pmu.irq_count + 1);
7878
}
7979

80-
void gen3_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs)
80+
void gen2_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs)
8181
{
8282
intel_uncore_write(uncore, regs.imr, 0xffffffff);
8383
intel_uncore_posting_read(uncore, regs.imr);
@@ -94,7 +94,7 @@ void gen3_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs)
9494
/*
9595
* We should clear IMR at preinstall/uninstall, and just check at postinstall.
9696
*/
97-
void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
97+
void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
9898
{
9999
u32 val = intel_uncore_read(uncore, reg);
100100

@@ -110,10 +110,10 @@ void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
110110
intel_uncore_posting_read(uncore, reg);
111111
}
112112

113-
void gen3_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
113+
void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
114114
u32 imr_val, u32 ier_val)
115115
{
116-
gen3_assert_iir_is_zero(uncore, regs.iir);
116+
gen2_assert_iir_is_zero(uncore, regs.iir);
117117

118118
intel_uncore_write(uncore, regs.ier, ier_val);
119119
intel_uncore_write(uncore, regs.imr, imr_val);
@@ -622,7 +622,7 @@ static void ibx_irq_reset(struct drm_i915_private *dev_priv)
622622
if (HAS_PCH_NOP(dev_priv))
623623
return;
624624

625-
gen3_irq_reset(uncore, SDE_IRQ_REGS);
625+
gen2_irq_reset(uncore, SDE_IRQ_REGS);
626626

627627
if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
628628
intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff);
@@ -634,7 +634,7 @@ static void ilk_irq_reset(struct drm_i915_private *dev_priv)
634634
{
635635
struct intel_uncore *uncore = &dev_priv->uncore;
636636

637-
gen3_irq_reset(uncore, DE_IRQ_REGS);
637+
gen2_irq_reset(uncore, DE_IRQ_REGS);
638638
dev_priv->irq_mask = ~0u;
639639

640640
if (GRAPHICS_VER(dev_priv) == 7)
@@ -671,7 +671,7 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
671671

672672
gen8_gt_irq_reset(to_gt(dev_priv));
673673
gen8_display_irq_reset(dev_priv);
674-
gen3_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
674+
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
675675

676676
if (HAS_PCH_SPLIT(dev_priv))
677677
ibx_irq_reset(dev_priv);
@@ -688,8 +688,8 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
688688
gen11_gt_irq_reset(gt);
689689
gen11_display_irq_reset(dev_priv);
690690

691-
gen3_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
692-
gen3_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
691+
gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
692+
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
693693
}
694694

695695
static void dg1_irq_reset(struct drm_i915_private *dev_priv)
@@ -705,8 +705,8 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv)
705705

706706
gen11_display_irq_reset(dev_priv);
707707

708-
gen3_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
709-
gen3_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
708+
gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
709+
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
710710

711711
intel_uncore_write(uncore, GEN11_GFX_MSTR_IRQ, ~0);
712712
}
@@ -720,7 +720,7 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
720720

721721
gen8_gt_irq_reset(to_gt(dev_priv));
722722

723-
gen3_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
723+
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
724724

725725
spin_lock_irq(&dev_priv->irq_lock);
726726
if (dev_priv->display.irq.display_irqs_enabled)
@@ -765,7 +765,7 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
765765
gen11_gt_irq_postinstall(gt);
766766
gen11_de_irq_postinstall(dev_priv);
767767

768-
gen3_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
768+
gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
769769

770770
gen11_master_intr_enable(intel_uncore_regs(uncore));
771771
intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);
@@ -781,7 +781,7 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
781781
for_each_gt(gt, dev_priv, i)
782782
gen11_gt_irq_postinstall(gt);
783783

784-
gen3_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
784+
gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
785785

786786
dg1_de_irq_postinstall(dev_priv);
787787

@@ -869,7 +869,7 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv)
869869

870870
i9xx_display_irq_reset(dev_priv);
871871

872-
gen3_irq_reset(uncore, GEN2_IRQ_REGS);
872+
gen2_irq_reset(uncore, GEN2_IRQ_REGS);
873873
dev_priv->irq_mask = ~0u;
874874
}
875875

@@ -901,7 +901,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
901901
enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
902902
}
903903

904-
gen3_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask);
904+
gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask);
905905

906906
/* Interrupt setup is already guaranteed to be single-threaded, this is
907907
* just to make the assert_spin_locked check happy. */
@@ -974,7 +974,7 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv)
974974

975975
i9xx_display_irq_reset(dev_priv);
976976

977-
gen3_irq_reset(uncore, GEN2_IRQ_REGS);
977+
gen2_irq_reset(uncore, GEN2_IRQ_REGS);
978978
dev_priv->irq_mask = ~0u;
979979
}
980980

@@ -1022,7 +1022,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
10221022
if (IS_G4X(dev_priv))
10231023
enable_mask |= I915_BSD_USER_INTERRUPT;
10241024

1025-
gen3_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask);
1025+
gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask);
10261026

10271027
/* Interrupt setup is already guaranteed to be single-threaded, this is
10281028
* just to make the assert_spin_locked check happy. */

‎drivers/gpu/drm/i915/i915_irq.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -40,11 +40,11 @@ bool intel_irqs_enabled(struct drm_i915_private *dev_priv);
4040
void intel_synchronize_irq(struct drm_i915_private *i915);
4141
void intel_synchronize_hardirq(struct drm_i915_private *i915);
4242

43-
void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg);
43+
void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg);
4444

45-
void gen3_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs);
45+
void gen2_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs);
4646

47-
void gen3_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
47+
void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
4848
u32 imr_val, u32 ier_val);
4949

5050
#endif /* __I915_IRQ_H__ */

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