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Alex Elderdavem330
Alex Elder
authored and
davem330
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net: ipa: define IPA v3.1 GSI interrupt register offsets
Add definitions of the offsets for IRQ-related GSI registers. Use gsi_reg() rather than the corresponding GSI_CNTXT_*_OFFSET() macros to get the offsets for these registers, and get rid of the macros. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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+195
-102
lines changed

3 files changed

+195
-102
lines changed

‎drivers/net/ipa/gsi.c‎

Lines changed: 119 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -221,8 +221,10 @@ static u32 ev_ch_e_cntxt_1_length_encode(enum ipa_version version, u32 length)
221221
/* Update the GSI IRQ type register with the cached value */
222222
static void gsi_irq_type_update(struct gsi *gsi, u32 val)
223223
{
224+
const struct reg *reg = gsi_reg(gsi, CNTXT_TYPE_IRQ_MSK);
225+
224226
gsi->type_enabled_bitmap = val;
225-
iowrite32(val, gsi->virt + GSI_CNTXT_TYPE_IRQ_MSK_OFFSET);
227+
iowrite32(val, gsi->virt + reg_offset(reg));
226228
}
227229

228230
static void gsi_irq_type_enable(struct gsi *gsi, enum gsi_irq_type_id type_id)
@@ -243,22 +245,29 @@ static void gsi_irq_type_disable(struct gsi *gsi, enum gsi_irq_type_id type_id)
243245
static void gsi_irq_ev_ctrl_enable(struct gsi *gsi, u32 evt_ring_id)
244246
{
245247
u32 val = BIT(evt_ring_id);
248+
const struct reg *reg;
246249

247250
/* There's a small chance that a previous command completed
248251
* after the interrupt was disabled, so make sure we have no
249252
* pending interrupts before we enable them.
250253
*/
251-
iowrite32(~0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET);
254+
reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ_CLR);
255+
iowrite32(~0, gsi->virt + reg_offset(reg));
252256

253-
iowrite32(val, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET);
257+
reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ_MSK);
258+
iowrite32(val, gsi->virt + reg_offset(reg));
254259
gsi_irq_type_enable(gsi, GSI_EV_CTRL);
255260
}
256261

257262
/* Disable event ring control interrupts */
258263
static void gsi_irq_ev_ctrl_disable(struct gsi *gsi)
259264
{
265+
const struct reg *reg;
266+
260267
gsi_irq_type_disable(gsi, GSI_EV_CTRL);
261-
iowrite32(0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET);
268+
269+
reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ_MSK);
270+
iowrite32(0, gsi->virt + reg_offset(reg));
262271
}
263272

264273
/* Channel commands are performed one at a time. Their completion is
@@ -269,32 +278,43 @@ static void gsi_irq_ev_ctrl_disable(struct gsi *gsi)
269278
static void gsi_irq_ch_ctrl_enable(struct gsi *gsi, u32 channel_id)
270279
{
271280
u32 val = BIT(channel_id);
281+
const struct reg *reg;
272282

273283
/* There's a small chance that a previous command completed
274284
* after the interrupt was disabled, so make sure we have no
275285
* pending interrupts before we enable them.
276286
*/
277-
iowrite32(~0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET);
287+
reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ_CLR);
288+
iowrite32(~0, gsi->virt + reg_offset(reg));
289+
290+
reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ_MSK);
291+
iowrite32(val, gsi->virt + reg_offset(reg));
278292

279-
iowrite32(val, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET);
280293
gsi_irq_type_enable(gsi, GSI_CH_CTRL);
281294
}
282295

283296
/* Disable channel control interrupts */
284297
static void gsi_irq_ch_ctrl_disable(struct gsi *gsi)
285298
{
299+
const struct reg *reg;
300+
286301
gsi_irq_type_disable(gsi, GSI_CH_CTRL);
287-
iowrite32(0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET);
302+
303+
reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ_MSK);
304+
iowrite32(0, gsi->virt + reg_offset(reg));
288305
}
289306

290307
static void gsi_irq_ieob_enable_one(struct gsi *gsi, u32 evt_ring_id)
291308
{
292309
bool enable_ieob = !gsi->ieob_enabled_bitmap;
310+
const struct reg *reg;
293311
u32 val;
294312

295313
gsi->ieob_enabled_bitmap |= BIT(evt_ring_id);
314+
315+
reg = gsi_reg(gsi, CNTXT_SRC_IEOB_IRQ_MSK);
296316
val = gsi->ieob_enabled_bitmap;
297-
iowrite32(val, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET);
317+
iowrite32(val, gsi->virt + reg_offset(reg));
298318

299319
/* Enable the interrupt type if this is the first channel enabled */
300320
if (enable_ieob)
@@ -303,6 +323,7 @@ static void gsi_irq_ieob_enable_one(struct gsi *gsi, u32 evt_ring_id)
303323

304324
static void gsi_irq_ieob_disable(struct gsi *gsi, u32 event_mask)
305325
{
326+
const struct reg *reg;
306327
u32 val;
307328

308329
gsi->ieob_enabled_bitmap &= ~event_mask;
@@ -311,8 +332,9 @@ static void gsi_irq_ieob_disable(struct gsi *gsi, u32 event_mask)
311332
if (!gsi->ieob_enabled_bitmap)
312333
gsi_irq_type_disable(gsi, GSI_IEOB);
313334

335+
reg = gsi_reg(gsi, CNTXT_SRC_IEOB_IRQ_MSK);
314336
val = gsi->ieob_enabled_bitmap;
315-
iowrite32(val, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET);
337+
iowrite32(val, gsi->virt + reg_offset(reg));
316338
}
317339

318340
static void gsi_irq_ieob_disable_one(struct gsi *gsi, u32 evt_ring_id)
@@ -323,34 +345,44 @@ static void gsi_irq_ieob_disable_one(struct gsi *gsi, u32 evt_ring_id)
323345
/* Enable all GSI_interrupt types */
324346
static void gsi_irq_enable(struct gsi *gsi)
325347
{
348+
const struct reg *reg;
326349
u32 val;
327350

328351
/* Global interrupts include hardware error reports. Enable
329352
* that so we can at least report the error should it occur.
330353
*/
331-
iowrite32(ERROR_INT, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
354+
reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_EN);
355+
iowrite32(ERROR_INT, gsi->virt + reg_offset(reg));
356+
332357
gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | GSI_GLOB_EE);
333358

334359
/* General GSI interrupts are reported to all EEs; if they occur
335360
* they are unrecoverable (without reset). A breakpoint interrupt
336361
* also exists, but we don't support that. We want to be notified
337362
* of errors so we can report them, even if they can't be handled.
338363
*/
364+
reg = gsi_reg(gsi, CNTXT_GSI_IRQ_EN);
339365
val = BUS_ERROR;
340366
val |= CMD_FIFO_OVRFLOW;
341367
val |= MCS_STACK_OVRFLOW;
342-
iowrite32(val, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET);
368+
iowrite32(val, gsi->virt + reg_offset(reg));
369+
343370
gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | GSI_GENERAL);
344371
}
345372

346373
/* Disable all GSI interrupt types */
347374
static void gsi_irq_disable(struct gsi *gsi)
348375
{
376+
const struct reg *reg;
377+
349378
gsi_irq_type_update(gsi, 0);
350379

351380
/* Clear the type-specific interrupt masks set by gsi_irq_enable() */
352-
iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET);
353-
iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
381+
reg = gsi_reg(gsi, CNTXT_GSI_IRQ_EN);
382+
iowrite32(0, gsi->virt + reg_offset(reg));
383+
384+
reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_EN);
385+
iowrite32(0, gsi->virt + reg_offset(reg));
354386
}
355387

356388
/* Return the virtual address associated with a ring index */
@@ -1120,10 +1152,14 @@ static void gsi_trans_tx_completed(struct gsi_trans *trans)
11201152
/* Channel control interrupt handler */
11211153
static void gsi_isr_chan_ctrl(struct gsi *gsi)
11221154
{
1155+
const struct reg *reg;
11231156
u32 channel_mask;
11241157

1125-
channel_mask = ioread32(gsi->virt + GSI_CNTXT_SRC_CH_IRQ_OFFSET);
1126-
iowrite32(channel_mask, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET);
1158+
reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ);
1159+
channel_mask = ioread32(gsi->virt + reg_offset(reg));
1160+
1161+
reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ_CLR);
1162+
iowrite32(channel_mask, gsi->virt + reg_offset(reg));
11271163

11281164
while (channel_mask) {
11291165
u32 channel_id = __ffs(channel_mask);
@@ -1137,10 +1173,14 @@ static void gsi_isr_chan_ctrl(struct gsi *gsi)
11371173
/* Event ring control interrupt handler */
11381174
static void gsi_isr_evt_ctrl(struct gsi *gsi)
11391175
{
1176+
const struct reg *reg;
11401177
u32 event_mask;
11411178

1142-
event_mask = ioread32(gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET);
1143-
iowrite32(event_mask, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET);
1179+
reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ);
1180+
event_mask = ioread32(gsi->virt + reg_offset(reg));
1181+
1182+
reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ_CLR);
1183+
iowrite32(event_mask, gsi->virt + reg_offset(reg));
11441184

11451185
while (event_mask) {
11461186
u32 evt_ring_id = __ffs(event_mask);
@@ -1215,6 +1255,7 @@ static void gsi_isr_glob_err(struct gsi *gsi)
12151255
/* Generic EE interrupt handler */
12161256
static void gsi_isr_gp_int1(struct gsi *gsi)
12171257
{
1258+
const struct reg *reg;
12181259
u32 result;
12191260
u32 val;
12201261

@@ -1237,7 +1278,8 @@ static void gsi_isr_gp_int1(struct gsi *gsi)
12371278
* In either case, we silently ignore a INCORRECT_CHANNEL_STATE
12381279
* error if we receive it.
12391280
*/
1240-
val = ioread32(gsi->virt + GSI_CNTXT_SCRATCH_0_OFFSET);
1281+
reg = gsi_reg(gsi, CNTXT_SCRATCH_0);
1282+
val = ioread32(gsi->virt + reg_offset(reg));
12411283
result = u32_get_bits(val, GENERIC_EE_RESULT_FMASK);
12421284

12431285
switch (result) {
@@ -1262,14 +1304,17 @@ static void gsi_isr_gp_int1(struct gsi *gsi)
12621304
/* Inter-EE interrupt handler */
12631305
static void gsi_isr_glob_ee(struct gsi *gsi)
12641306
{
1307+
const struct reg *reg;
12651308
u32 val;
12661309

1267-
val = ioread32(gsi->virt + GSI_CNTXT_GLOB_IRQ_STTS_OFFSET);
1310+
reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_STTS);
1311+
val = ioread32(gsi->virt + reg_offset(reg));
12681312

12691313
if (val & ERROR_INT)
12701314
gsi_isr_glob_err(gsi);
12711315

1272-
iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_CLR_OFFSET);
1316+
reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_CLR);
1317+
iowrite32(val, gsi->virt + reg_offset(reg));
12731318

12741319
val &= ~ERROR_INT;
12751320

@@ -1285,11 +1330,16 @@ static void gsi_isr_glob_ee(struct gsi *gsi)
12851330
/* I/O completion interrupt event */
12861331
static void gsi_isr_ieob(struct gsi *gsi)
12871332
{
1333+
const struct reg *reg;
12881334
u32 event_mask;
12891335

1290-
event_mask = ioread32(gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_OFFSET);
1336+
reg = gsi_reg(gsi, CNTXT_SRC_IEOB_IRQ);
1337+
event_mask = ioread32(gsi->virt + reg_offset(reg));
1338+
12911339
gsi_irq_ieob_disable(gsi, event_mask);
1292-
iowrite32(event_mask, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET);
1340+
1341+
reg = gsi_reg(gsi, CNTXT_SRC_IEOB_IRQ_CLR);
1342+
iowrite32(event_mask, gsi->virt + reg_offset(reg));
12931343

12941344
while (event_mask) {
12951345
u32 evt_ring_id = __ffs(event_mask);
@@ -1304,10 +1354,14 @@ static void gsi_isr_ieob(struct gsi *gsi)
13041354
static void gsi_isr_general(struct gsi *gsi)
13051355
{
13061356
struct device *dev = gsi->dev;
1357+
const struct reg *reg;
13071358
u32 val;
13081359

1309-
val = ioread32(gsi->virt + GSI_CNTXT_GSI_IRQ_STTS_OFFSET);
1310-
iowrite32(val, gsi->virt + GSI_CNTXT_GSI_IRQ_CLR_OFFSET);
1360+
reg = gsi_reg(gsi, CNTXT_GSI_IRQ_STTS);
1361+
val = ioread32(gsi->virt + reg_offset(reg));
1362+
1363+
reg = gsi_reg(gsi, CNTXT_GSI_IRQ_CLR);
1364+
iowrite32(val, gsi->virt + reg_offset(reg));
13111365

13121366
dev_err(dev, "unexpected general interrupt 0x%08x\n", val);
13131367
}
@@ -1323,17 +1377,25 @@ static void gsi_isr_general(struct gsi *gsi)
13231377
static irqreturn_t gsi_isr(int irq, void *dev_id)
13241378
{
13251379
struct gsi *gsi = dev_id;
1380+
const struct reg *reg;
13261381
u32 intr_mask;
13271382
u32 cnt = 0;
1383+
u32 offset;
1384+
1385+
reg = gsi_reg(gsi, CNTXT_TYPE_IRQ);
1386+
offset = reg_offset(reg);
13281387

13291388
/* enum gsi_irq_type_id defines GSI interrupt types */
1330-
while ((intr_mask = ioread32(gsi->virt + GSI_CNTXT_TYPE_IRQ_OFFSET))) {
1389+
while ((intr_mask = ioread32(gsi->virt + offset))) {
13311390
/* intr_mask contains bitmask of pending GSI interrupts */
13321391
do {
13331392
u32 gsi_intr = BIT(__ffs(intr_mask));
13341393

13351394
intr_mask ^= gsi_intr;
13361395

1396+
/* Note: the IRQ condition for each type is cleared
1397+
* when the type-specific register is updated.
1398+
*/
13371399
switch (gsi_intr) {
13381400
case GSI_CH_CTRL:
13391401
gsi_isr_chan_ctrl(gsi);
@@ -1717,7 +1779,9 @@ static int gsi_generic_command(struct gsi *gsi, u32 channel_id,
17171779
enum gsi_generic_cmd_opcode opcode,
17181780
u8 params)
17191781
{
1782+
const struct reg *reg;
17201783
bool timeout;
1784+
u32 offset;
17211785
u32 val;
17221786

17231787
/* The error global interrupt type is always enabled (until we tear
@@ -1729,13 +1793,17 @@ static int gsi_generic_command(struct gsi *gsi, u32 channel_id,
17291793
* channel), and only from this function. So we enable the GP_INT1
17301794
* IRQ type here, and disable it again after the command completes.
17311795
*/
1796+
reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_EN);
17321797
val = ERROR_INT | GP_INT1;
1733-
iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
1798+
iowrite32(val, gsi->virt + reg_offset(reg));
17341799

17351800
/* First zero the result code field */
1736-
val = ioread32(gsi->virt + GSI_CNTXT_SCRATCH_0_OFFSET);
1801+
reg = gsi_reg(gsi, CNTXT_SCRATCH_0);
1802+
offset = reg_offset(reg);
1803+
val = ioread32(gsi->virt + offset);
1804+
17371805
val &= ~GENERIC_EE_RESULT_FMASK;
1738-
iowrite32(val, gsi->virt + GSI_CNTXT_SCRATCH_0_OFFSET);
1806+
iowrite32(val, gsi->virt + offset);
17391807

17401808
/* Now issue the command */
17411809
val = u32_encode_bits(opcode, GENERIC_OPCODE_FMASK);
@@ -1747,7 +1815,8 @@ static int gsi_generic_command(struct gsi *gsi, u32 channel_id,
17471815
timeout = !gsi_command(gsi, GSI_GENERIC_CMD_OFFSET, val);
17481816

17491817
/* Disable the GP_INT1 IRQ type again */
1750-
iowrite32(ERROR_INT, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
1818+
reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_EN);
1819+
iowrite32(ERROR_INT, gsi->virt + reg_offset(reg));
17511820

17521821
if (!timeout)
17531822
return gsi->result;
@@ -1904,32 +1973,41 @@ static void gsi_channel_teardown(struct gsi *gsi)
19041973
/* Turn off all GSI interrupts initially */
19051974
static int gsi_irq_setup(struct gsi *gsi)
19061975
{
1976+
const struct reg *reg;
19071977
int ret;
19081978

19091979
/* Writing 1 indicates IRQ interrupts; 0 would be MSI */
1910-
iowrite32(1, gsi->virt + GSI_CNTXT_INTSET_OFFSET);
1980+
reg = gsi_reg(gsi, CNTXT_INTSET);
1981+
iowrite32(1, gsi->virt + reg_offset(reg));
19111982

19121983
/* Disable all interrupt types */
19131984
gsi_irq_type_update(gsi, 0);
19141985

19151986
/* Clear all type-specific interrupt masks */
1916-
iowrite32(0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET);
1917-
iowrite32(0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET);
1918-
iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
1919-
iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET);
1987+
reg = gsi_reg(gsi, CNTXT_SRC_CH_IRQ_MSK);
1988+
iowrite32(0, gsi->virt + reg_offset(reg));
1989+
1990+
reg = gsi_reg(gsi, CNTXT_SRC_EV_CH_IRQ_MSK);
1991+
iowrite32(0, gsi->virt + reg_offset(reg));
1992+
1993+
reg = gsi_reg(gsi, CNTXT_GLOB_IRQ_EN);
1994+
iowrite32(0, gsi->virt + reg_offset(reg));
1995+
1996+
reg = gsi_reg(gsi, CNTXT_SRC_IEOB_IRQ_MSK);
1997+
iowrite32(0, gsi->virt + reg_offset(reg));
19201998

19211999
/* The inter-EE interrupts are not supported for IPA v3.0-v3.1 */
19222000
if (gsi->version > IPA_VERSION_3_1) {
1923-
u32 offset;
1924-
19252001
/* These registers are in the non-adjusted address range */
1926-
offset = GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET;
1927-
iowrite32(0, gsi->virt_raw + offset);
1928-
offset = GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET;
1929-
iowrite32(0, gsi->virt_raw + offset);
2002+
reg = gsi_reg(gsi, INTER_EE_SRC_CH_IRQ_MSK);
2003+
iowrite32(0, gsi->virt_raw + reg_offset(reg));
2004+
2005+
reg = gsi_reg(gsi, INTER_EE_SRC_EV_CH_IRQ_MSK);
2006+
iowrite32(0, gsi->virt_raw + reg_offset(reg));
19302007
}
19312008

1932-
iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET);
2009+
reg = gsi_reg(gsi, CNTXT_GSI_IRQ_EN);
2010+
iowrite32(0, gsi->virt + reg_offset(reg));
19332011

19342012
ret = request_irq(gsi->irq, gsi_isr, 0, "gsi", gsi);
19352013
if (ret)

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