Skip to content

Commit 8345a71

Browse files
Lijo Lazaralexdeucher
Lijo Lazar
authored and
alexdeucher
committed
drm/amdgpu: Add more checks to PSP mailbox
Instead of checking the response flag, use status mask also to check against any unexpected failures like a device drop. Also, log error if waiting on a psp response fails/times out. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 5562b66 commit 8345a71

File tree

9 files changed

+107
-61
lines changed

9 files changed

+107
-61
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -597,6 +597,10 @@ int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
597597
udelay(1);
598598
}
599599

600+
dev_err(adev->dev,
601+
"psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x",
602+
reg_index, mask, val, reg_val);
603+
600604
return -ETIME;
601605
}
602606

‎drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,17 @@
5151
#define C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_HI 0x10
5252
#define C2PMSG_CMD_SPI_GET_FLASH_IMAGE 0x11
5353

54+
/* Command register bit 31 set to indicate readiness */
55+
#define MBOX_TOS_READY_FLAG (GFX_FLAG_RESPONSE)
56+
#define MBOX_TOS_READY_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK)
57+
58+
/* Values to check for a successful GFX_CMD response wait. Check against
59+
* both status bits and response state - helps to detect a command failure
60+
* or other unexpected cases like a device drop reading all 0xFFs
61+
*/
62+
#define MBOX_TOS_RESP_FLAG (GFX_FLAG_RESPONSE)
63+
#define MBOX_TOS_RESP_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK)
64+
5465
extern const struct attribute_group amdgpu_flash_attr_group;
5566

5667
enum psp_shared_mem_size {

‎drivers/gpu/drm/amd/amdgpu/psp_v10_0.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,7 @@ static int psp_v10_0_ring_create(struct psp_context *psp,
9494

9595
/* Wait for response flag (bit 31) in C2PMSG_64 */
9696
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
97-
0x80000000, 0x8000FFFF, false);
97+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
9898

9999
return ret;
100100
}
@@ -115,7 +115,7 @@ static int psp_v10_0_ring_stop(struct psp_context *psp,
115115

116116
/* Wait for response flag (bit 31) in C2PMSG_64 */
117117
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
118-
0x80000000, 0x80000000, false);
118+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
119119

120120
return ret;
121121
}

‎drivers/gpu/drm/amd/amdgpu/psp_v11_0.c‎

Lines changed: 19 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -277,11 +277,13 @@ static int psp_v11_0_ring_stop(struct psp_context *psp,
277277

278278
/* Wait for response flag (bit 31) */
279279
if (amdgpu_sriov_vf(adev))
280-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
281-
0x80000000, 0x80000000, false);
280+
ret = psp_wait_for(
281+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
282+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
282283
else
283-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
284-
0x80000000, 0x80000000, false);
284+
ret = psp_wait_for(
285+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
286+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
285287

286288
return ret;
287289
}
@@ -317,13 +319,15 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
317319
mdelay(20);
318320

319321
/* Wait for response flag (bit 31) in C2PMSG_101 */
320-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
321-
0x80000000, 0x8000FFFF, false);
322+
ret = psp_wait_for(
323+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
324+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
322325

323326
} else {
324327
/* Wait for sOS ready for ring creation */
325-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
326-
0x80000000, 0x80000000, false);
328+
ret = psp_wait_for(
329+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
330+
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
327331
if (ret) {
328332
DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
329333
return ret;
@@ -347,8 +351,9 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
347351
mdelay(20);
348352

349353
/* Wait for response flag (bit 31) in C2PMSG_64 */
350-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
351-
0x80000000, 0x8000FFFF, false);
354+
ret = psp_wait_for(
355+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
356+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
352357
}
353358

354359
return ret;
@@ -381,7 +386,8 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp)
381386

382387
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
383388

384-
ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
389+
ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG,
390+
MBOX_TOS_READY_MASK, false);
385391

386392
if (ret) {
387393
DRM_INFO("psp is not working correctly before mode1 reset!\n");
@@ -395,7 +401,8 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp)
395401

396402
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
397403

398-
ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
404+
ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK,
405+
false);
399406

400407
if (ret) {
401408
DRM_INFO("psp mode 1 reset failed!\n");

‎drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c‎

Lines changed: 15 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -41,17 +41,19 @@ static int psp_v11_0_8_ring_stop(struct psp_context *psp,
4141
/* there might be handshake issue with hardware which needs delay */
4242
mdelay(20);
4343
/* Wait for response flag (bit 31) */
44-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
45-
0x80000000, 0x80000000, false);
44+
ret = psp_wait_for(
45+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
46+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
4647
} else {
4748
/* Write the ring destroy command*/
4849
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
4950
GFX_CTRL_CMD_ID_DESTROY_RINGS);
5051
/* there might be handshake issue with hardware which needs delay */
5152
mdelay(20);
5253
/* Wait for response flag (bit 31) */
53-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
54-
0x80000000, 0x80000000, false);
54+
ret = psp_wait_for(
55+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
56+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
5557
}
5658

5759
return ret;
@@ -87,13 +89,15 @@ static int psp_v11_0_8_ring_create(struct psp_context *psp,
8789
mdelay(20);
8890

8991
/* Wait for response flag (bit 31) in C2PMSG_101 */
90-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
91-
0x80000000, 0x8000FFFF, false);
92+
ret = psp_wait_for(
93+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
94+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
9295

9396
} else {
9497
/* Wait for sOS ready for ring creation */
95-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
96-
0x80000000, 0x80000000, false);
98+
ret = psp_wait_for(
99+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
100+
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
97101
if (ret) {
98102
DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
99103
return ret;
@@ -117,8 +121,9 @@ static int psp_v11_0_8_ring_create(struct psp_context *psp,
117121
mdelay(20);
118122

119123
/* Wait for response flag (bit 31) in C2PMSG_64 */
120-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
121-
0x80000000, 0x8000FFFF, false);
124+
ret = psp_wait_for(
125+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
126+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
122127
}
123128

124129
return ret;

‎drivers/gpu/drm/amd/amdgpu/psp_v12_0.c‎

Lines changed: 11 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -163,7 +163,7 @@ static int psp_v12_0_ring_create(struct psp_context *psp,
163163

164164
/* Wait for response flag (bit 31) in C2PMSG_64 */
165165
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
166-
0x80000000, 0x8000FFFF, false);
166+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
167167

168168
return ret;
169169
}
@@ -184,11 +184,13 @@ static int psp_v12_0_ring_stop(struct psp_context *psp,
184184

185185
/* Wait for response flag (bit 31) */
186186
if (amdgpu_sriov_vf(adev))
187-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
188-
0x80000000, 0x80000000, false);
187+
ret = psp_wait_for(
188+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
189+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
189190
else
190-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
191-
0x80000000, 0x80000000, false);
191+
ret = psp_wait_for(
192+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
193+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
192194

193195
return ret;
194196
}
@@ -219,7 +221,8 @@ static int psp_v12_0_mode1_reset(struct psp_context *psp)
219221

220222
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
221223

222-
ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
224+
ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG,
225+
MBOX_TOS_READY_MASK, false);
223226

224227
if (ret) {
225228
DRM_INFO("psp is not working correctly before mode1 reset!\n");
@@ -233,7 +236,8 @@ static int psp_v12_0_mode1_reset(struct psp_context *psp)
233236

234237
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
235238

236-
ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
239+
ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK,
240+
false);
237241

238242
if (ret) {
239243
DRM_INFO("psp mode 1 reset failed!\n");

‎drivers/gpu/drm/amd/amdgpu/psp_v13_0.c‎

Lines changed: 15 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -384,17 +384,19 @@ static int psp_v13_0_ring_stop(struct psp_context *psp,
384384
/* there might be handshake issue with hardware which needs delay */
385385
mdelay(20);
386386
/* Wait for response flag (bit 31) */
387-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
388-
0x80000000, 0x80000000, false);
387+
ret = psp_wait_for(
388+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
389+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
389390
} else {
390391
/* Write the ring destroy command*/
391392
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
392393
GFX_CTRL_CMD_ID_DESTROY_RINGS);
393394
/* there might be handshake issue with hardware which needs delay */
394395
mdelay(20);
395396
/* Wait for response flag (bit 31) */
396-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
397-
0x80000000, 0x80000000, false);
397+
ret = psp_wait_for(
398+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
399+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
398400
}
399401

400402
return ret;
@@ -430,13 +432,15 @@ static int psp_v13_0_ring_create(struct psp_context *psp,
430432
mdelay(20);
431433

432434
/* Wait for response flag (bit 31) in C2PMSG_101 */
433-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
434-
0x80000000, 0x8000FFFF, false);
435+
ret = psp_wait_for(
436+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
437+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
435438

436439
} else {
437440
/* Wait for sOS ready for ring creation */
438-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
439-
0x80000000, 0x80000000, false);
441+
ret = psp_wait_for(
442+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
443+
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
440444
if (ret) {
441445
DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
442446
return ret;
@@ -460,8 +464,9 @@ static int psp_v13_0_ring_create(struct psp_context *psp,
460464
mdelay(20);
461465

462466
/* Wait for response flag (bit 31) in C2PMSG_64 */
463-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
464-
0x80000000, 0x8000FFFF, false);
467+
ret = psp_wait_for(
468+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
469+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
465470
}
466471

467472
return ret;

‎drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c‎

Lines changed: 15 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -204,17 +204,19 @@ static int psp_v13_0_4_ring_stop(struct psp_context *psp,
204204
/* there might be handshake issue with hardware which needs delay */
205205
mdelay(20);
206206
/* Wait for response flag (bit 31) */
207-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
208-
0x80000000, 0x80000000, false);
207+
ret = psp_wait_for(
208+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
209+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
209210
} else {
210211
/* Write the ring destroy command*/
211212
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
212213
GFX_CTRL_CMD_ID_DESTROY_RINGS);
213214
/* there might be handshake issue with hardware which needs delay */
214215
mdelay(20);
215216
/* Wait for response flag (bit 31) */
216-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
217-
0x80000000, 0x80000000, false);
217+
ret = psp_wait_for(
218+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
219+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
218220
}
219221

220222
return ret;
@@ -250,13 +252,15 @@ static int psp_v13_0_4_ring_create(struct psp_context *psp,
250252
mdelay(20);
251253

252254
/* Wait for response flag (bit 31) in C2PMSG_101 */
253-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
254-
0x80000000, 0x8000FFFF, false);
255+
ret = psp_wait_for(
256+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
257+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
255258

256259
} else {
257260
/* Wait for sOS ready for ring creation */
258-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
259-
0x80000000, 0x80000000, false);
261+
ret = psp_wait_for(
262+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
263+
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
260264
if (ret) {
261265
DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
262266
return ret;
@@ -280,8 +284,9 @@ static int psp_v13_0_4_ring_create(struct psp_context *psp,
280284
mdelay(20);
281285

282286
/* Wait for response flag (bit 31) in C2PMSG_64 */
283-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
284-
0x80000000, 0x8000FFFF, false);
287+
ret = psp_wait_for(
288+
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
289+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
285290
}
286291

287292
return ret;

‎drivers/gpu/drm/amd/amdgpu/psp_v14_0.c‎

Lines changed: 15 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -248,17 +248,19 @@ static int psp_v14_0_ring_stop(struct psp_context *psp,
248248
/* there might be handshake issue with hardware which needs delay */
249249
mdelay(20);
250250
/* Wait for response flag (bit 31) */
251-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
252-
0x80000000, 0x80000000, false);
251+
ret = psp_wait_for(
252+
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
253+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
253254
} else {
254255
/* Write the ring destroy command*/
255256
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64,
256257
GFX_CTRL_CMD_ID_DESTROY_RINGS);
257258
/* there might be handshake issue with hardware which needs delay */
258259
mdelay(20);
259260
/* Wait for response flag (bit 31) */
260-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
261-
0x80000000, 0x80000000, false);
261+
ret = psp_wait_for(
262+
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
263+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
262264
}
263265

264266
return ret;
@@ -294,13 +296,15 @@ static int psp_v14_0_ring_create(struct psp_context *psp,
294296
mdelay(20);
295297

296298
/* Wait for response flag (bit 31) in C2PMSG_101 */
297-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
298-
0x80000000, 0x8000FFFF, false);
299+
ret = psp_wait_for(
300+
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
301+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
299302

300303
} else {
301304
/* Wait for sOS ready for ring creation */
302-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
303-
0x80000000, 0x80000000, false);
305+
ret = psp_wait_for(
306+
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
307+
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
304308
if (ret) {
305309
DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
306310
return ret;
@@ -324,8 +328,9 @@ static int psp_v14_0_ring_create(struct psp_context *psp,
324328
mdelay(20);
325329

326330
/* Wait for response flag (bit 31) in C2PMSG_64 */
327-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
328-
0x80000000, 0x8000FFFF, false);
331+
ret = psp_wait_for(
332+
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
333+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
329334
}
330335

331336
return ret;

0 commit comments

Comments
 (0)