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jnikulajnikula
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drm/i915/display: convert i915_pipestat_enable_mask() to struct intel_display
Going forward, struct intel_display is the main display device data pointer. Convert i915_pipestat_enable_mask() to struct intel_display, allowing further conversions elsewhere. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/975b382c703cfb62f24643e40eac247b8e8bbea8.1739378096.git.jani.nikula@intel.com
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3 files changed

+15
-13
lines changed

3 files changed

+15
-13
lines changed

‎drivers/gpu/drm/i915/display/intel_display_irq.c‎

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -226,29 +226,30 @@ void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits)
226226
ibx_display_interrupt_update(i915, bits, 0);
227227
}
228228

229-
u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
229+
u32 i915_pipestat_enable_mask(struct intel_display *display,
230230
enum pipe pipe)
231231
{
232-
u32 status_mask = dev_priv->display.irq.pipestat_irq_mask[pipe];
232+
struct drm_i915_private *dev_priv = to_i915(display->drm);
233+
u32 status_mask = display->irq.pipestat_irq_mask[pipe];
233234
u32 enable_mask = status_mask << 16;
234235

235236
lockdep_assert_held(&dev_priv->irq_lock);
236237

237-
if (DISPLAY_VER(dev_priv) < 5)
238+
if (DISPLAY_VER(display) < 5)
238239
goto out;
239240

240241
/*
241242
* On pipe A we don't support the PSR interrupt yet,
242243
* on pipe B and C the same bit MBZ.
243244
*/
244-
if (drm_WARN_ON_ONCE(&dev_priv->drm,
245+
if (drm_WARN_ON_ONCE(display->drm,
245246
status_mask & PIPE_A_PSR_STATUS_VLV))
246247
return 0;
247248
/*
248249
* On pipe B and C we don't support the PSR interrupt yet, on pipe
249250
* A the same bit is for perf counters which we don't use either.
250251
*/
251-
if (drm_WARN_ON_ONCE(&dev_priv->drm,
252+
if (drm_WARN_ON_ONCE(display->drm,
252253
status_mask & PIPE_B_PSR_STATUS_VLV))
253254
return 0;
254255

@@ -261,7 +262,7 @@ u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
261262
enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
262263

263264
out:
264-
drm_WARN_ONCE(&dev_priv->drm,
265+
drm_WARN_ONCE(display->drm,
265266
enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
266267
status_mask & ~PIPESTAT_INT_STATUS_MASK,
267268
"pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
@@ -288,7 +289,7 @@ void i915_enable_pipestat(struct drm_i915_private *dev_priv,
288289
return;
289290

290291
dev_priv->display.irq.pipestat_irq_mask[pipe] |= status_mask;
291-
enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
292+
enable_mask = i915_pipestat_enable_mask(display, pipe);
292293

293294
intel_de_write(display, reg, enable_mask | status_mask);
294295
intel_de_posting_read(display, reg);
@@ -312,7 +313,7 @@ void i915_disable_pipestat(struct drm_i915_private *dev_priv,
312313
return;
313314

314315
dev_priv->display.irq.pipestat_irq_mask[pipe] &= ~status_mask;
315-
enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
316+
enable_mask = i915_pipestat_enable_mask(display, pipe);
316317

317318
intel_de_write(display, reg, enable_mask | status_mask);
318319
intel_de_posting_read(display, reg);
@@ -525,7 +526,7 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
525526

526527
reg = PIPESTAT(dev_priv, pipe);
527528
pipe_stats[pipe] = intel_de_read(display, reg) & status_mask;
528-
enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
529+
enable_mask = i915_pipestat_enable_mask(display, pipe);
529530

530531
/*
531532
* Clear the PIPE*STAT regs before the IIR

‎drivers/gpu/drm/i915/display/intel_display_irq.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,9 @@
1111
#include "intel_display_limits.h"
1212

1313
enum pipe;
14-
struct drm_i915_private;
1514
struct drm_crtc;
15+
struct drm_i915_private;
16+
struct intel_display;
1617

1718
void valleyview_enable_display_irqs(struct drm_i915_private *i915);
1819
void valleyview_disable_display_irqs(struct drm_i915_private *i915);
@@ -64,7 +65,7 @@ void gen8_de_irq_postinstall(struct drm_i915_private *i915);
6465
void gen11_de_irq_postinstall(struct drm_i915_private *i915);
6566
void dg1_de_irq_postinstall(struct drm_i915_private *i915);
6667

67-
u32 i915_pipestat_enable_mask(struct drm_i915_private *i915, enum pipe pipe);
68+
u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
6869
void i915_enable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask);
6970
void i915_disable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask);
7071
void i915_enable_asle_pipestat(struct drm_i915_private *i915);

‎drivers/gpu/drm/i915/display/intel_fifo_underrun.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -103,7 +103,7 @@ static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
103103
if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
104104
return;
105105

106-
enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);
106+
enable_mask = i915_pipestat_enable_mask(display, crtc->pipe);
107107
intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
108108
intel_de_posting_read(display, reg);
109109

@@ -121,7 +121,7 @@ static void i9xx_set_fifo_underrun_reporting(struct intel_display *display,
121121
lockdep_assert_held(&dev_priv->irq_lock);
122122

123123
if (enable) {
124-
u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
124+
u32 enable_mask = i915_pipestat_enable_mask(display, pipe);
125125

126126
intel_de_write(display, reg,
127127
enable_mask | PIPE_FIFO_UNDERRUN_STATUS);

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