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Pingchao Yangherbertx
Pingchao Yang
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herbertx
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crypto: qat - add support for new devices to FW loader
FW loader updates for new qat devices Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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7 files changed

+823
-85
lines changed

7 files changed

+823
-85
lines changed

‎drivers/crypto/qat/qat_common/adf_accel_engine.c‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -78,9 +78,12 @@ int adf_ae_fw_load(struct adf_accel_dev *accel_dev)
7878
uof_addr = (void *)loader_data->uof_fw->data;
7979
mmp_size = loader_data->mmp_fw->size;
8080
mmp_addr = (void *)loader_data->mmp_fw->data;
81-
qat_uclo_wr_mimage(loader_data->fw_loader, mmp_addr, mmp_size);
82-
if (qat_uclo_map_uof_obj(loader_data->fw_loader, uof_addr, uof_size)) {
83-
dev_err(&GET_DEV(accel_dev), "Failed to map UOF\n");
81+
if (qat_uclo_wr_mimage(loader_data->fw_loader, mmp_addr, mmp_size)) {
82+
dev_err(&GET_DEV(accel_dev), "Failed to load MMP\n");
83+
goto out_err;
84+
}
85+
if (qat_uclo_map_obj(loader_data->fw_loader, uof_addr, uof_size)) {
86+
dev_err(&GET_DEV(accel_dev), "Failed to map FW\n");
8487
goto out_err;
8588
}
8689
if (qat_uclo_wr_all_uimage(loader_data->fw_loader)) {

‎drivers/crypto/qat/qat_common/adf_common_drv.h‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -178,6 +178,8 @@ void qat_hal_reset(struct icp_qat_fw_loader_handle *handle);
178178
int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle);
179179
void qat_hal_set_live_ctx(struct icp_qat_fw_loader_handle *handle,
180180
unsigned char ae, unsigned int ctx_mask);
181+
int qat_hal_check_ae_active(struct icp_qat_fw_loader_handle *handle,
182+
unsigned int ae);
181183
int qat_hal_set_ae_lm_mode(struct icp_qat_fw_loader_handle *handle,
182184
unsigned char ae, enum icp_qat_uof_regtype lm_type,
183185
unsigned char mode);
@@ -216,10 +218,10 @@ int qat_hal_wr_lm(struct icp_qat_fw_loader_handle *handle,
216218
unsigned char ae, unsigned short lm_addr, unsigned int value);
217219
int qat_uclo_wr_all_uimage(struct icp_qat_fw_loader_handle *handle);
218220
void qat_uclo_del_uof_obj(struct icp_qat_fw_loader_handle *handle);
219-
int qat_uclo_map_uof_obj(struct icp_qat_fw_loader_handle *handle,
220-
void *addr_ptr, int mem_size);
221-
void qat_uclo_wr_mimage(struct icp_qat_fw_loader_handle *handle,
222-
void *addr_ptr, int mem_size);
221+
int qat_uclo_wr_mimage(struct icp_qat_fw_loader_handle *handle, void *addr_ptr,
222+
int mem_size);
223+
int qat_uclo_map_obj(struct icp_qat_fw_loader_handle *handle,
224+
void *addr_ptr, int mem_size);
223225
#if defined(CONFIG_PCI_IOV)
224226
int adf_sriov_configure(struct pci_dev *pdev, int numvfs);
225227
void adf_disable_sriov(struct adf_accel_dev *accel_dev);

‎drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,11 +68,21 @@ struct icp_qat_fw_loader_hal_handle {
6868

6969
struct icp_qat_fw_loader_handle {
7070
struct icp_qat_fw_loader_hal_handle *hal_handle;
71+
struct pci_dev *pci_dev;
7172
void *obj_handle;
73+
void *sobj_handle;
74+
bool fw_auth;
7275
void __iomem *hal_sram_addr_v;
7376
void __iomem *hal_cap_g_ctl_csr_addr_v;
7477
void __iomem *hal_cap_ae_xfer_csr_addr_v;
7578
void __iomem *hal_cap_ae_local_csr_addr_v;
7679
void __iomem *hal_ep_csr_addr_v;
7780
};
81+
82+
struct icp_firml_dram_desc {
83+
void __iomem *dram_base_addr;
84+
void *dram_base_addr_v;
85+
dma_addr_t dram_bus_addr;
86+
u64 dram_size;
87+
};
7888
#endif

‎drivers/crypto/qat/qat_common/icp_qat_hal.h‎

Lines changed: 34 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,31 @@ enum hal_ae_csr {
8181
LOCAL_CSR_STATUS = 0x180,
8282
};
8383

84+
enum fcu_csr {
85+
FCU_CONTROL = 0x8c0,
86+
FCU_STATUS = 0x8c4,
87+
FCU_STATUS1 = 0x8c8,
88+
FCU_DRAM_ADDR_LO = 0x8cc,
89+
FCU_DRAM_ADDR_HI = 0x8d0,
90+
FCU_RAMBASE_ADDR_HI = 0x8d4,
91+
FCU_RAMBASE_ADDR_LO = 0x8d8
92+
};
93+
94+
enum fcu_cmd {
95+
FCU_CTRL_CMD_NOOP = 0,
96+
FCU_CTRL_CMD_AUTH = 1,
97+
FCU_CTRL_CMD_LOAD = 2,
98+
FCU_CTRL_CMD_START = 3
99+
};
100+
101+
enum fcu_sts {
102+
FCU_STS_NO_STS = 0,
103+
FCU_STS_VERI_DONE = 1,
104+
FCU_STS_LOAD_DONE = 2,
105+
FCU_STS_VERI_FAIL = 3,
106+
FCU_STS_LOAD_FAIL = 4,
107+
FCU_STS_BUSY = 5
108+
};
84109
#define UA_ECS (0x1 << 31)
85110
#define ACS_ABO_BITPOS 31
86111
#define ACS_ACNO 0x7
@@ -98,6 +123,13 @@ enum hal_ae_csr {
98123
#define LCS_STATUS (0x1)
99124
#define MMC_SHARE_CS_BITPOS 2
100125
#define GLOBAL_CSR 0xA00
126+
#define FCU_CTRL_AE_POS 0x8
127+
#define FCU_AUTH_STS_MASK 0x7
128+
#define FCU_STS_DONE_POS 0x9
129+
#define FCU_STS_AUTHFWLD_POS 0X8
130+
#define FCU_LOADED_AE_POS 0x16
131+
#define FW_AUTH_WAIT_PERIOD 10
132+
#define FW_AUTH_MAX_RETRY 300
101133

102134
#define SET_CAP_CSR(handle, csr, val) \
103135
ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val)
@@ -106,20 +138,19 @@ enum hal_ae_csr {
106138
#define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val)
107139
#define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr)
108140
#define AE_CSR(handle, ae) \
109-
(handle->hal_cap_ae_local_csr_addr_v + \
141+
((char __iomem *)handle->hal_cap_ae_local_csr_addr_v + \
110142
((ae & handle->hal_handle->ae_mask) << 12))
111143
#define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & csr))
112144
#define SET_AE_CSR(handle, ae, csr, val) \
113145
ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
114146
#define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)
115147
#define AE_XFER(handle, ae) \
116-
(handle->hal_cap_ae_xfer_csr_addr_v + \
148+
((char __iomem *)handle->hal_cap_ae_xfer_csr_addr_v + \
117149
((ae & handle->hal_handle->ae_mask) << 12))
118150
#define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \
119151
((reg & 0xff) << 2))
120152
#define SET_AE_XFER(handle, ae, reg, val) \
121153
ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val)
122154
#define SRAM_WRITE(handle, addr, val) \
123155
ADF_CSR_WR(handle->hal_sram_addr_v, addr, val)
124-
#define SRAM_READ(handle, addr) ADF_CSR_RD(handle->hal_sram_addr_v, addr)
125156
#endif

‎drivers/crypto/qat/qat_common/icp_qat_uclo.h‎

Lines changed: 158 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -47,32 +47,55 @@
4747
#ifndef __ICP_QAT_UCLO_H__
4848
#define __ICP_QAT_UCLO_H__
4949

50-
#define ICP_QAT_AC_C_CPU_TYPE 0x00400000
50+
#define ICP_QAT_AC_895XCC_DEV_TYPE 0x00400000
51+
#define ICP_QAT_AC_C62X_DEV_TYPE 0x01000000
52+
#define ICP_QAT_AC_C3XXX_DEV_TYPE 0x02000000
5153
#define ICP_QAT_UCLO_MAX_AE 12
5254
#define ICP_QAT_UCLO_MAX_CTX 8
5355
#define ICP_QAT_UCLO_MAX_UIMAGE (ICP_QAT_UCLO_MAX_AE * ICP_QAT_UCLO_MAX_CTX)
5456
#define ICP_QAT_UCLO_MAX_USTORE 0x4000
5557
#define ICP_QAT_UCLO_MAX_XFER_REG 128
5658
#define ICP_QAT_UCLO_MAX_GPR_REG 128
57-
#define ICP_QAT_UCLO_MAX_NN_REG 128
5859
#define ICP_QAT_UCLO_MAX_LMEM_REG 1024
5960
#define ICP_QAT_UCLO_AE_ALL_CTX 0xff
6061
#define ICP_QAT_UOF_OBJID_LEN 8
6162
#define ICP_QAT_UOF_FID 0xc6c2
6263
#define ICP_QAT_UOF_MAJVER 0x4
6364
#define ICP_QAT_UOF_MINVER 0x11
64-
#define ICP_QAT_UOF_NN_MODE_NOTCARE 0xff
6565
#define ICP_QAT_UOF_OBJS "UOF_OBJS"
6666
#define ICP_QAT_UOF_STRT "UOF_STRT"
67-
#define ICP_QAT_UOF_GTID "UOF_GTID"
6867
#define ICP_QAT_UOF_IMAG "UOF_IMAG"
6968
#define ICP_QAT_UOF_IMEM "UOF_IMEM"
70-
#define ICP_QAT_UOF_MSEG "UOF_MSEG"
7169
#define ICP_QAT_UOF_LOCAL_SCOPE 1
7270
#define ICP_QAT_UOF_INIT_EXPR 0
7371
#define ICP_QAT_UOF_INIT_REG 1
7472
#define ICP_QAT_UOF_INIT_REG_CTX 2
7573
#define ICP_QAT_UOF_INIT_EXPR_ENDIAN_SWAP 3
74+
#define ICP_QAT_SUOF_OBJ_ID_LEN 8
75+
#define ICP_QAT_SUOF_FID 0x53554f46
76+
#define ICP_QAT_SUOF_MAJVER 0x0
77+
#define ICP_QAT_SUOF_MINVER 0x1
78+
#define ICP_QAT_SIMG_AE_INIT_SEQ_LEN (50 * sizeof(unsigned long long))
79+
#define ICP_QAT_SIMG_AE_INSTS_LEN (0x4000 * sizeof(unsigned long long))
80+
#define ICP_QAT_CSS_FWSK_MODULUS_LEN 256
81+
#define ICP_QAT_CSS_FWSK_EXPONENT_LEN 4
82+
#define ICP_QAT_CSS_FWSK_PAD_LEN 252
83+
#define ICP_QAT_CSS_FWSK_PUB_LEN (ICP_QAT_CSS_FWSK_MODULUS_LEN + \
84+
ICP_QAT_CSS_FWSK_EXPONENT_LEN + \
85+
ICP_QAT_CSS_FWSK_PAD_LEN)
86+
#define ICP_QAT_CSS_SIGNATURE_LEN 256
87+
#define ICP_QAT_CSS_AE_IMG_LEN (sizeof(struct icp_qat_simg_ae_mode) + \
88+
ICP_QAT_SIMG_AE_INIT_SEQ_LEN + \
89+
ICP_QAT_SIMG_AE_INSTS_LEN)
90+
#define ICP_QAT_CSS_AE_SIMG_LEN (sizeof(struct icp_qat_css_hdr) + \
91+
ICP_QAT_CSS_FWSK_PUB_LEN + \
92+
ICP_QAT_CSS_SIGNATURE_LEN + \
93+
ICP_QAT_CSS_AE_IMG_LEN)
94+
#define ICP_QAT_AE_IMG_OFFSET (sizeof(struct icp_qat_css_hdr) + \
95+
ICP_QAT_CSS_FWSK_MODULUS_LEN + \
96+
ICP_QAT_CSS_FWSK_EXPONENT_LEN + \
97+
ICP_QAT_CSS_SIGNATURE_LEN)
98+
#define ICP_QAT_CSS_MAX_IMAGE_LEN 0x40000
7699

77100
#define ICP_QAT_CTX_MODE(ae_mode) ((ae_mode) & 0xf)
78101
#define ICP_QAT_NN_MODE(ae_mode) (((ae_mode) >> 0x4) & 0xf)
@@ -112,6 +135,11 @@ enum icp_qat_uof_regtype {
112135
ICP_NEIGH_REL,
113136
};
114137

138+
enum icp_qat_css_fwtype {
139+
CSS_AE_FIRMWARE = 0,
140+
CSS_MMP_FIRMWARE = 1
141+
};
142+
115143
struct icp_qat_uclo_page {
116144
struct icp_qat_uclo_encap_page *encap_page;
117145
struct icp_qat_uclo_region *region;
@@ -235,7 +263,7 @@ struct icp_qat_uof_filechunkhdr {
235263
};
236264

237265
struct icp_qat_uof_objhdr {
238-
unsigned int cpu_type;
266+
unsigned int ac_dev_type;
239267
unsigned short min_cpu_ver;
240268
unsigned short max_cpu_ver;
241269
short max_chunks;
@@ -326,7 +354,7 @@ struct icp_qat_uof_image {
326354
unsigned int img_name;
327355
unsigned int ae_assigned;
328356
unsigned int ctx_assigned;
329-
unsigned int cpu_type;
357+
unsigned int ac_dev_type;
330358
unsigned int entry_address;
331359
unsigned int fill_pattern[2];
332360
unsigned int reloadable_size;
@@ -374,4 +402,127 @@ struct icp_qat_uof_batch_init {
374402
unsigned int size;
375403
struct icp_qat_uof_batch_init *next;
376404
};
405+
406+
struct icp_qat_suof_img_hdr {
407+
char *simg_buf;
408+
unsigned long simg_len;
409+
char *css_header;
410+
char *css_key;
411+
char *css_signature;
412+
char *css_simg;
413+
unsigned long simg_size;
414+
unsigned int ae_num;
415+
unsigned int ae_mask;
416+
unsigned int fw_type;
417+
unsigned long simg_name;
418+
unsigned long appmeta_data;
419+
};
420+
421+
struct icp_qat_suof_img_tbl {
422+
unsigned int num_simgs;
423+
struct icp_qat_suof_img_hdr *simg_hdr;
424+
};
425+
426+
struct icp_qat_suof_handle {
427+
unsigned int file_id;
428+
unsigned int check_sum;
429+
char min_ver;
430+
char maj_ver;
431+
char fw_type;
432+
char *suof_buf;
433+
unsigned int suof_size;
434+
char *sym_str;
435+
unsigned int sym_size;
436+
struct icp_qat_suof_img_tbl img_table;
437+
};
438+
439+
struct icp_qat_fw_auth_desc {
440+
unsigned int img_len;
441+
unsigned int reserved;
442+
unsigned int css_hdr_high;
443+
unsigned int css_hdr_low;
444+
unsigned int img_high;
445+
unsigned int img_low;
446+
unsigned int signature_high;
447+
unsigned int signature_low;
448+
unsigned int fwsk_pub_high;
449+
unsigned int fwsk_pub_low;
450+
unsigned int img_ae_mode_data_high;
451+
unsigned int img_ae_mode_data_low;
452+
unsigned int img_ae_init_data_high;
453+
unsigned int img_ae_init_data_low;
454+
unsigned int img_ae_insts_high;
455+
unsigned int img_ae_insts_low;
456+
};
457+
458+
struct icp_qat_auth_chunk {
459+
struct icp_qat_fw_auth_desc fw_auth_desc;
460+
u64 chunk_size;
461+
u64 chunk_bus_addr;
462+
};
463+
464+
struct icp_qat_css_hdr {
465+
unsigned int module_type;
466+
unsigned int header_len;
467+
unsigned int header_ver;
468+
unsigned int module_id;
469+
unsigned int module_vendor;
470+
unsigned int date;
471+
unsigned int size;
472+
unsigned int key_size;
473+
unsigned int module_size;
474+
unsigned int exponent_size;
475+
unsigned int fw_type;
476+
unsigned int reserved[21];
477+
};
478+
479+
struct icp_qat_simg_ae_mode {
480+
unsigned int file_id;
481+
unsigned short maj_ver;
482+
unsigned short min_ver;
483+
unsigned int dev_type;
484+
unsigned short devmax_ver;
485+
unsigned short devmin_ver;
486+
unsigned int ae_mask;
487+
unsigned int ctx_enables;
488+
char fw_type;
489+
char ctx_mode;
490+
char nn_mode;
491+
char lm0_mode;
492+
char lm1_mode;
493+
char scs_mode;
494+
char lm2_mode;
495+
char lm3_mode;
496+
char tindex_mode;
497+
unsigned char reserved[7];
498+
char simg_name[256];
499+
char appmeta_data[256];
500+
};
501+
502+
struct icp_qat_suof_filehdr {
503+
unsigned int file_id;
504+
unsigned int check_sum;
505+
char min_ver;
506+
char maj_ver;
507+
char fw_type;
508+
char reserved;
509+
unsigned short max_chunks;
510+
unsigned short num_chunks;
511+
};
512+
513+
struct icp_qat_suof_chunk_hdr {
514+
char chunk_id[ICP_QAT_SUOF_OBJ_ID_LEN];
515+
u64 offset;
516+
u64 size;
517+
};
518+
519+
struct icp_qat_suof_strtable {
520+
unsigned int tab_length;
521+
unsigned int strings;
522+
};
523+
524+
struct icp_qat_suof_objhdr {
525+
unsigned int img_length;
526+
unsigned int reserved;
527+
};
377528
#endif

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