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phy: qcom-qmp-pcie: rename regs layout arrays
Rename regs layouts to follow the QMP PHY version. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-5-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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‎drivers/phy/qualcomm/phy-qcom-qmp-pcie.c‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -74,21 +74,14 @@ enum qphy_reg_layout {
7474
QPHY_LAYOUT_SIZE
7575
};
7676

77-
static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
78-
[QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
79-
[QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
80-
[QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
81-
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
82-
};
83-
84-
static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
77+
static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
8578
[QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
8679
[QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
8780
[QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS,
8881
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL,
8982
};
9083

91-
static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
84+
static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
9285
[QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
9386
[QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
9487
[QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
@@ -102,13 +95,20 @@ static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
10295
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
10396
};
10497

105-
static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
98+
static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
10699
[QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
107100
[QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
108101
[QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
109102
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
110103
};
111104

105+
static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
106+
[QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
107+
[QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
108+
[QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
109+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
110+
};
111+
112112
static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
113113
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
114114
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
@@ -1678,7 +1678,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
16781678
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
16791679
.vreg_list = NULL,
16801680
.num_vregs = 0,
1681-
.regs = pciephy_regs_layout,
1681+
.regs = pciephy_v2_regs_layout,
16821682

16831683
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
16841684
.phy_status = PHYSTATUS,
@@ -1705,7 +1705,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
17051705
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
17061706
.vreg_list = NULL,
17071707
.num_vregs = 0,
1708-
.regs = ipq_pciephy_gen3_regs_layout,
1708+
.regs = pciephy_v4_regs_layout,
17091709

17101710
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
17111711
.phy_status = PHYSTATUS,
@@ -1734,7 +1734,7 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
17341734
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
17351735
.vreg_list = NULL,
17361736
.num_vregs = 0,
1737-
.regs = ipq_pciephy_gen3_regs_layout,
1737+
.regs = pciephy_v4_regs_layout,
17381738

17391739
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
17401740
.phy_status = PHYSTATUS,
@@ -1761,7 +1761,7 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
17611761
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
17621762
.vreg_list = qmp_phy_vreg_l,
17631763
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1764-
.regs = sdm845_qmp_pciephy_regs_layout,
1764+
.regs = pciephy_v3_regs_layout,
17651765

17661766
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
17671767
.phy_status = PHYSTATUS,
@@ -1823,7 +1823,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
18231823
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
18241824
.vreg_list = qmp_phy_vreg_l,
18251825
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1826-
.regs = sm8250_pcie_regs_layout,
1826+
.regs = pciephy_v4_regs_layout,
18271827

18281828
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
18291829
.phy_status = PHYSTATUS,
@@ -1860,7 +1860,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
18601860
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
18611861
.vreg_list = qmp_phy_vreg_l,
18621862
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1863-
.regs = sm8250_pcie_regs_layout,
1863+
.regs = pciephy_v4_regs_layout,
18641864

18651865
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
18661866
.phy_status = PHYSTATUS,
@@ -1885,7 +1885,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
18851885
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
18861886
.vreg_list = qmp_phy_vreg_l,
18871887
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1888-
.regs = pciephy_regs_layout,
1888+
.regs = pciephy_v3_regs_layout,
18891889

18901890
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
18911891
.phy_status = PHYSTATUS,
@@ -1914,7 +1914,7 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
19141914
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
19151915
.vreg_list = qmp_phy_vreg_l,
19161916
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1917-
.regs = sm8250_pcie_regs_layout,
1917+
.regs = pciephy_v4_regs_layout,
19181918

19191919
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
19201920
.phy_status = PHYSTATUS,
@@ -1949,7 +1949,7 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = {
19491949
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
19501950
.vreg_list = qmp_phy_vreg_l,
19511951
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1952-
.regs = sm8250_pcie_regs_layout,
1952+
.regs = pciephy_v5_regs_layout,
19531953

19541954
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
19551955
.phy_status = PHYSTATUS,
@@ -1984,7 +1984,7 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = {
19841984
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
19851985
.vreg_list = qmp_phy_vreg_l,
19861986
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1987-
.regs = sm8250_pcie_regs_layout,
1987+
.regs = pciephy_v5_regs_layout,
19881988

19891989
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
19901990
.phy_status = PHYSTATUS,
@@ -2022,7 +2022,7 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = {
20222022
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
20232023
.vreg_list = qmp_phy_vreg_l,
20242024
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2025-
.regs = sm8250_pcie_regs_layout,
2025+
.regs = pciephy_v5_regs_layout,
20262026

20272027
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
20282028
.phy_status = PHYSTATUS,
@@ -2049,7 +2049,7 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
20492049
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
20502050
.vreg_list = qmp_phy_vreg_l,
20512051
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2052-
.regs = sm8250_pcie_regs_layout,
2052+
.regs = pciephy_v4_regs_layout,
20532053

20542054
.pwrdn_ctrl = SW_PWRDN,
20552055
.phy_status = PHYSTATUS_4_20,
@@ -2086,7 +2086,7 @@ static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = {
20862086
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
20872087
.vreg_list = qmp_phy_vreg_l,
20882088
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2089-
.regs = sm8250_pcie_regs_layout,
2089+
.regs = pciephy_v5_regs_layout,
20902090

20912091
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
20922092
.phy_status = PHYSTATUS,
@@ -2123,7 +2123,7 @@ static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = {
21232123
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
21242124
.vreg_list = qmp_phy_vreg_l,
21252125
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2126-
.regs = sm8250_pcie_regs_layout,
2126+
.regs = pciephy_v5_regs_layout,
21272127

21282128
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
21292129
.phy_status = PHYSTATUS,
@@ -2158,7 +2158,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
21582158
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
21592159
.vreg_list = qmp_phy_vreg_l,
21602160
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2161-
.regs = sm8250_pcie_regs_layout,
2161+
.regs = pciephy_v4_regs_layout,
21622162

21632163
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
21642164
.phy_status = PHYSTATUS,
@@ -2200,7 +2200,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
22002200
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
22012201
.vreg_list = qmp_phy_vreg_l,
22022202
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2203-
.regs = sm8250_pcie_regs_layout,
2203+
.regs = pciephy_v5_regs_layout,
22042204

22052205
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
22062206
.phy_status = PHYSTATUS_4_20,

‎drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,10 @@
77
#define QCOM_PHY_QMP_PCS_V5_H_
88

99
/* Only for QMP V5 PHY - USB/PCIe PCS registers */
10+
#define QPHY_V5_PCS_SW_RESET 0x000
11+
#define QPHY_V5_PCS_PCS_STATUS1 0x014
12+
#define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040
13+
#define QPHY_V5_PCS_START_CONTROL 0x044
1014
#define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4
1115
#define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8
1216
#define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc

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