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alexdeucheralexdeucher
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drm/amdgpu: clean up GC reset functions
Make them consistent and use the reset flags. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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5 files changed

+45
-26
lines changed

5 files changed

+45
-26
lines changed

‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4952,11 +4952,15 @@ static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
49524952
}
49534953
}
49544954
}
4955-
/* TODO: Add queue reset mask when FW fully supports it */
4955+
49564956
adev->gfx.gfx_supported_reset =
49574957
amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);
49584958
adev->gfx.compute_supported_reset =
49594959
amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);
4960+
if (!amdgpu_sriov_vf(adev)) {
4961+
adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
4962+
adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
4963+
}
49604964

49614965
r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);
49624966
if (r) {
@@ -9534,8 +9538,8 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring,
95349538
u64 addr;
95359539
int r;
95369540

9537-
if (amdgpu_sriov_vf(adev))
9538-
return -EINVAL;
9541+
if (!(adev->gfx.gfx_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
9542+
return -EOPNOTSUPP;
95399543

95409544
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
95419545
return -EINVAL;
@@ -9607,8 +9611,8 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
96079611
unsigned long flags;
96089612
int i, r;
96099613

9610-
if (amdgpu_sriov_vf(adev))
9611-
return -EINVAL;
9614+
if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
9615+
return -EOPNOTSUPP;
96129616

96139617
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
96149618
return -EINVAL;

‎drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c‎

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1806,12 +1806,17 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
18061806
case IP_VERSION(11, 0, 2):
18071807
case IP_VERSION(11, 0, 3):
18081808
if ((adev->gfx.me_fw_version >= 2280) &&
1809-
(adev->gfx.mec_fw_version >= 2410)) {
1810-
adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1811-
adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1809+
(adev->gfx.mec_fw_version >= 2410) &&
1810+
!amdgpu_sriov_vf(adev)) {
1811+
adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1812+
adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
18121813
}
18131814
break;
18141815
default:
1816+
if (!amdgpu_sriov_vf(adev)) {
1817+
adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1818+
adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1819+
}
18151820
break;
18161821
}
18171822

@@ -6818,8 +6823,8 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring,
68186823
struct amdgpu_device *adev = ring->adev;
68196824
int r;
68206825

6821-
if (amdgpu_sriov_vf(adev))
6822-
return -EINVAL;
6826+
if (!(adev->gfx.gfx_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
6827+
return -EOPNOTSUPP;
68236828

68246829
drm_sched_wqueue_stop(&ring->sched);
68256830

@@ -6989,8 +6994,8 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring,
69896994
struct amdgpu_device *adev = ring->adev;
69906995
int r = 0;
69916996

6992-
if (amdgpu_sriov_vf(adev))
6993-
return -EINVAL;
6997+
if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
6998+
return -EOPNOTSUPP;
69946999

69957000
drm_sched_wqueue_stop(&ring->sched);
69967001

‎drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c‎

Lines changed: 11 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1542,10 +1542,14 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
15421542
case IP_VERSION(12, 0, 0):
15431543
case IP_VERSION(12, 0, 1):
15441544
if ((adev->gfx.me_fw_version >= 2660) &&
1545-
(adev->gfx.mec_fw_version >= 2920)) {
1546-
adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1547-
adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1545+
(adev->gfx.mec_fw_version >= 2920) &&
1546+
!amdgpu_sriov_vf(adev)) {
1547+
adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1548+
adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
15481549
}
1550+
break;
1551+
default:
1552+
break;
15491553
}
15501554

15511555
if (!adev->enable_mes_kiq) {
@@ -5314,8 +5318,8 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring,
53145318
struct amdgpu_device *adev = ring->adev;
53155319
int r;
53165320

5317-
if (amdgpu_sriov_vf(adev))
5318-
return -EINVAL;
5321+
if (!(adev->gfx.gfx_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
5322+
return -EOPNOTSUPP;
53195323

53205324
drm_sched_wqueue_stop(&ring->sched);
53215325

@@ -5437,8 +5441,8 @@ static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring,
54375441
struct amdgpu_device *adev = ring->adev;
54385442
int r;
54395443

5440-
if (amdgpu_sriov_vf(adev))
5441-
return -EINVAL;
5444+
if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
5445+
return -EOPNOTSUPP;
54425446

54435447
drm_sched_wqueue_stop(&ring->sched);
54445448

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2410,6 +2410,8 @@ static int gfx_v9_0_sw_init(struct amdgpu_ip_block *ip_block)
24102410
amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);
24112411
adev->gfx.compute_supported_reset =
24122412
amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);
2413+
if (!amdgpu_sriov_vf(adev))
2414+
adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
24132415

24142416
r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, 0);
24152417
if (r) {
@@ -7181,8 +7183,8 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring,
71817183
unsigned long flags;
71827184
int i, r;
71837185

7184-
if (amdgpu_sriov_vf(adev))
7185-
return -EINVAL;
7186+
if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
7187+
return -EOPNOTSUPP;
71867188

71877189
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
71887190
return -EINVAL;

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1148,13 +1148,15 @@ static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block)
11481148
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
11491149
case IP_VERSION(9, 4, 3):
11501150
case IP_VERSION(9, 4, 4):
1151-
if (adev->gfx.mec_fw_version >= 155) {
1151+
if ((adev->gfx.mec_fw_version >= 155) &&
1152+
!amdgpu_sriov_vf(adev)) {
11521153
adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
11531154
adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE;
11541155
}
11551156
break;
11561157
case IP_VERSION(9, 5, 0):
1157-
if (adev->gfx.mec_fw_version >= 21) {
1158+
if ((adev->gfx.mec_fw_version >= 21) &&
1159+
!amdgpu_sriov_vf(adev)) {
11581160
adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
11591161
adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE;
11601162
}
@@ -3561,8 +3563,8 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring,
35613563
unsigned long flags;
35623564
int r;
35633565

3564-
if (amdgpu_sriov_vf(adev))
3565-
return -EINVAL;
3566+
if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
3567+
return -EOPNOTSUPP;
35663568

35673569
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
35683570
return -EINVAL;
@@ -3594,7 +3596,9 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring,
35943596
dev_err(adev->dev, "fail to wait on hqd deactive and will try pipe reset\n");
35953597

35963598
pipe_reset:
3597-
if(r) {
3599+
if (r) {
3600+
if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_PIPE))
3601+
return -EOPNOTSUPP;
35983602
r = gfx_v9_4_3_reset_hw_pipe(ring);
35993603
dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name,
36003604
r ? "failed" : "successfully");

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