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drm/xe: Create a xe_gt_freq component for raw management and sysfs
Goals of this new xe_gt_freq component: 1. Detach sysfs controls and raw freq management from GuC SLPC. 2. Create a directory that could later be aligned with devfreq. 3. Encapsulate all the freq control in a single directory. Although we only have one freq domain per GT, already start with a numbered freq0 directory so it could be expanded in the future if multiple domains or PLL are needed. Note: Although in the goal #1, the raw freq management control is mentioned, this patch only starts by the sysfs control. The RP freq configuration and init freq selection are still under the guc_pc, but should be moved to this component in a follow-up patch. v2: - Add /tile# to the doc and remove unnecessary kobject_put (Riana) - s/ssize_t/int on some ret variables (Vinay) Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Cc: Riana Tauro <riana.tauro@intel.com> Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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‎drivers/gpu/drm/xe/Makefile‎

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@@ -73,6 +73,7 @@ xe-y += xe_bb.o \
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xe_gt_ccs_mode.o \
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xe_gt_clock.o \
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xe_gt_debugfs.o \
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xe_gt_freq.o \
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xe_gt_idle.o \
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xe_gt_mcr.o \
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xe_gt_pagefault.o \

‎drivers/gpu/drm/xe/xe_gt.c‎

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@@ -24,6 +24,7 @@
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#include "xe_gsc.h"
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#include "xe_gt_ccs_mode.h"
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#include "xe_gt_clock.h"
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#include "xe_gt_freq.h"
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#include "xe_gt_idle.h"
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#include "xe_gt_mcr.h"
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#include "xe_gt_pagefault.h"
@@ -511,6 +512,8 @@ int xe_gt_init(struct xe_gt *gt)
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if (err)
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return err;
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xe_gt_freq_init(gt);
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xe_force_wake_init_engines(gt, gt_to_fw(gt));
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err = all_fw_domain_init(gt);

‎drivers/gpu/drm/xe/xe_gt_freq.c‎

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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#include "xe_gt_freq.h"
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#include <linux/kobject.h>
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#include <linux/sysfs.h>
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#include <drm/drm_managed.h>
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#include <drm/drm_print.h>
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#include "xe_device_types.h"
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#include "xe_gt_sysfs.h"
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#include "xe_guc_pc.h"
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/**
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* DOC: Xe GT Frequency Management
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*
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* This component is responsible for the raw GT frequency management, including
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* the sysfs API.
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*
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* Underneath, Xe enables GuC SLPC automated frequency management. GuC is then
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* allowed to request PCODE any frequency between the Minimum and the Maximum
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* selected by this component. Furthermore, it is important to highlight that
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* PCODE is the ultimate decision maker of the actual running frequency, based
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* on thermal and other running conditions.
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*
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* Xe's Freq provides a sysfs API for frequency management:
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*
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* device/tile#/gt#/freq0/<item>_freq *read-only* files:
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* - act_freq: The actual resolved frequency decided by PCODE.
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* - cur_freq: The current one requested by GuC PC to the PCODE.
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* - rpn_freq: The Render Performance (RP) N level, which is the minimal one.
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* - rpe_freq: The Render Performance (RP) E level, which is the efficient one.
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* - rp0_freq: The Render Performance (RP) 0 level, which is the maximum one.
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*
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* device/tile#/gt#/freq0/<item>_freq *read-write* files:
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* - min_freq: Min frequency request.
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* - max_freq: Max frequency request.
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* If max <= min, then freq_min becomes a fixed frequency request.
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*/
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static struct xe_guc_pc *
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dev_to_pc(struct device *dev)
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{
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return &kobj_to_gt(dev->kobj.parent)->uc.guc.pc;
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}
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static ssize_t act_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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return sysfs_emit(buf, "%d\n", xe_guc_pc_get_act_freq(pc));
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}
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static DEVICE_ATTR_RO(act_freq);
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static ssize_t cur_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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u32 freq;
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ssize_t ret;
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ret = xe_guc_pc_get_cur_freq(pc, &freq);
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if (ret)
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return ret;
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return sysfs_emit(buf, "%d\n", freq);
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}
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static DEVICE_ATTR_RO(cur_freq);
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static ssize_t rp0_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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return sysfs_emit(buf, "%d\n", xe_guc_pc_get_rp0_freq(pc));
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}
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static DEVICE_ATTR_RO(rp0_freq);
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static ssize_t rpe_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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return sysfs_emit(buf, "%d\n", xe_guc_pc_get_rpe_freq(pc));
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}
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static DEVICE_ATTR_RO(rpe_freq);
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static ssize_t rpn_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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return sysfs_emit(buf, "%d\n", xe_guc_pc_get_rpn_freq(pc));
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}
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static DEVICE_ATTR_RO(rpn_freq);
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static ssize_t min_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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u32 freq;
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ssize_t ret;
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ret = xe_guc_pc_get_min_freq(pc, &freq);
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if (ret)
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return ret;
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return sysfs_emit(buf, "%d\n", freq);
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}
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static ssize_t min_freq_store(struct device *dev, struct device_attribute *attr,
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const char *buff, size_t count)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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u32 freq;
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ssize_t ret;
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ret = kstrtou32(buff, 0, &freq);
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if (ret)
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return ret;
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ret = xe_guc_pc_set_min_freq(pc, freq);
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if (ret)
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return ret;
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return count;
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}
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static DEVICE_ATTR_RW(min_freq);
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static ssize_t max_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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u32 freq;
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ssize_t ret;
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ret = xe_guc_pc_get_max_freq(pc, &freq);
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if (ret)
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return ret;
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return sysfs_emit(buf, "%d\n", freq);
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}
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static ssize_t max_freq_store(struct device *dev, struct device_attribute *attr,
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const char *buff, size_t count)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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u32 freq;
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ssize_t ret;
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ret = kstrtou32(buff, 0, &freq);
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if (ret)
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return ret;
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ret = xe_guc_pc_set_max_freq(pc, freq);
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if (ret)
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return ret;
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return count;
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}
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static DEVICE_ATTR_RW(max_freq);
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static const struct attribute *freq_attrs[] = {
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&dev_attr_act_freq.attr,
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&dev_attr_cur_freq.attr,
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&dev_attr_rp0_freq.attr,
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&dev_attr_rpe_freq.attr,
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&dev_attr_rpn_freq.attr,
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&dev_attr_min_freq.attr,
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&dev_attr_max_freq.attr,
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NULL
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};
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static void freq_fini(struct drm_device *drm, void *arg)
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{
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struct kobject *kobj = arg;
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sysfs_remove_files(kobj, freq_attrs);
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kobject_put(kobj);
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}
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/**
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* xe_gt_freq_init - Initialize Xe Freq component
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* @gt: Xe GT object
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*
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* It needs to be initialized after GT Sysfs and GuC PC components are ready.
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*/
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void xe_gt_freq_init(struct xe_gt *gt)
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{
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struct xe_device *xe = gt_to_xe(gt);
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int err;
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gt->freq = kobject_create_and_add("freq0", gt->sysfs);
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if (!gt->freq) {
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drm_warn(&xe->drm, "failed to add freq0 directory to %s, err: %d\n",
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kobject_name(gt->sysfs), err);
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return;
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}
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err = drmm_add_action_or_reset(&xe->drm, freq_fini, gt->freq);
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if (err) {
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drm_warn(&xe->drm, "%s: drmm_add_action_or_reset failed, err: %d\n",
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__func__, err);
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return;
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}
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err = sysfs_create_files(gt->freq, freq_attrs);
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if (err)
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drm_warn(&xe->drm, "failed to add freq attrs to %s, err: %d\n",
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kobject_name(gt->freq), err);
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}

‎drivers/gpu/drm/xe/xe_gt_freq.h‎

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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_GT_FREQ_H_
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#define _XE_GT_FREQ_H_
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struct xe_gt;
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void xe_gt_freq_init(struct xe_gt *gt);
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#endif

‎drivers/gpu/drm/xe/xe_gt_types.h‎

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@@ -307,6 +307,9 @@ struct xe_gt {
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/** @sysfs: sysfs' kobj used by xe_gt_sysfs */
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struct kobject *sysfs;
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/** @freq: Main GT freq sysfs control */
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struct kobject *freq;
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/** @mocs: info */
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struct {
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/** @uc_index: UC index */

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