@@ -302,7 +302,7 @@ static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
302302 MLX5_SET (mkc , mkc , access_mode_1_0 , MLX5_MKC_ACCESS_MODE_MTT );
303303 mlx5e_mkey_set_relaxed_ordering (mdev , mkc );
304304 MLX5_SET (mkc , mkc , qpn , 0xffffff );
305- MLX5_SET (mkc , mkc , pd , mdev -> mlx5e_res .pdn );
305+ MLX5_SET (mkc , mkc , pd , mdev -> mlx5e_res .hw_objs . pdn );
306306 MLX5_SET64 (mkc , mkc , len , npages << page_shift );
307307 MLX5_SET (mkc , mkc , translations_octword_size ,
308308 MLX5_MTT_OCTW (npages ));
@@ -1019,7 +1019,7 @@ static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
10191019 sq -> pdev = c -> pdev ;
10201020 sq -> mkey_be = c -> mkey_be ;
10211021 sq -> channel = c ;
1022- sq -> uar_map = mdev -> mlx5e_res .bfreg .map ;
1022+ sq -> uar_map = mdev -> mlx5e_res .hw_objs . bfreg .map ;
10231023 sq -> min_inline_mode = params -> tx_min_inline_mode ;
10241024 sq -> hw_mtu = MLX5E_SW2HW_MTU (params , params -> sw_mtu );
10251025 sq -> xsk_pool = xsk_pool ;
@@ -1090,7 +1090,7 @@ static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
10901090 int err ;
10911091
10921092 sq -> channel = c ;
1093- sq -> uar_map = mdev -> mlx5e_res .bfreg .map ;
1093+ sq -> uar_map = mdev -> mlx5e_res .hw_objs . bfreg .map ;
10941094
10951095 param -> wq .db_numa_node = cpu_to_node (c -> cpu );
10961096 err = mlx5_wq_cyc_create (mdev , & param -> wq , sqc_wq , wq , & sq -> wq_ctrl );
@@ -1174,7 +1174,7 @@ static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
11741174 sq -> priv = c -> priv ;
11751175 sq -> ch_ix = c -> ix ;
11761176 sq -> txq_ix = txq_ix ;
1177- sq -> uar_map = mdev -> mlx5e_res .bfreg .map ;
1177+ sq -> uar_map = mdev -> mlx5e_res .hw_objs . bfreg .map ;
11781178 sq -> min_inline_mode = params -> tx_min_inline_mode ;
11791179 sq -> hw_mtu = MLX5E_SW2HW_MTU (params , params -> sw_mtu );
11801180 INIT_WORK (& sq -> recover_work , mlx5e_tx_err_cqe_work );
@@ -1257,7 +1257,7 @@ static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
12571257 MLX5_SET (sqc , sqc , flush_in_error_en , 1 );
12581258
12591259 MLX5_SET (wq , wq , wq_type , MLX5_WQ_TYPE_CYCLIC );
1260- MLX5_SET (wq , wq , uar_page , mdev -> mlx5e_res .bfreg .index );
1260+ MLX5_SET (wq , wq , uar_page , mdev -> mlx5e_res .hw_objs . bfreg .index );
12611261 MLX5_SET (wq , wq , log_wq_pg_sz , csp -> wq_ctrl -> buf .page_shift -
12621262 MLX5_ADAPTER_PAGE_SHIFT );
12631263 MLX5_SET64 (wq , wq , dbr_addr , csp -> wq_ctrl -> db .dma );
@@ -2032,7 +2032,7 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
20322032 c -> cpu = cpu ;
20332033 c -> pdev = mlx5_core_dma_dev (priv -> mdev );
20342034 c -> netdev = priv -> netdev ;
2035- c -> mkey_be = cpu_to_be32 (priv -> mdev -> mlx5e_res .mkey .key );
2035+ c -> mkey_be = cpu_to_be32 (priv -> mdev -> mlx5e_res .hw_objs . mkey .key );
20362036 c -> num_tc = params -> num_tc ;
20372037 c -> xdp = !!params -> xdp_prog ;
20382038 c -> stats = & priv -> channel_stats [ix ].ch ;
@@ -2217,7 +2217,7 @@ void mlx5e_build_rq_param(struct mlx5e_priv *priv,
22172217 MLX5_SET (wq , wq , end_padding_mode , MLX5_WQ_END_PAD_MODE_ALIGN );
22182218 MLX5_SET (wq , wq , log_wq_stride ,
22192219 mlx5e_get_rqwq_log_stride (params -> rq_wq_type , ndsegs ));
2220- MLX5_SET (wq , wq , pd , mdev -> mlx5e_res .pdn );
2220+ MLX5_SET (wq , wq , pd , mdev -> mlx5e_res .hw_objs . pdn );
22212221 MLX5_SET (rqc , rqc , counter_set_id , priv -> q_counter );
22222222 MLX5_SET (rqc , rqc , vsd , params -> vlan_strip_disable );
22232223 MLX5_SET (rqc , rqc , scatter_fcs , params -> scatter_fcs_en );
@@ -2248,7 +2248,7 @@ void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
22482248 void * wq = MLX5_ADDR_OF (sqc , sqc , wq );
22492249
22502250 MLX5_SET (wq , wq , log_wq_stride , ilog2 (MLX5_SEND_WQE_BB ));
2251- MLX5_SET (wq , wq , pd , priv -> mdev -> mlx5e_res .pdn );
2251+ MLX5_SET (wq , wq , pd , priv -> mdev -> mlx5e_res .hw_objs . pdn );
22522252
22532253 param -> wq .buf_numa_node = dev_to_node (mlx5_core_dma_dev (priv -> mdev ));
22542254}
@@ -3421,10 +3421,10 @@ int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
34213421{
34223422 void * tisc = MLX5_ADDR_OF (create_tis_in , in , ctx );
34233423
3424- MLX5_SET (tisc , tisc , transport_domain , mdev -> mlx5e_res .td .tdn );
3424+ MLX5_SET (tisc , tisc , transport_domain , mdev -> mlx5e_res .hw_objs . td .tdn );
34253425
34263426 if (MLX5_GET (tisc , tisc , tls_en ))
3427- MLX5_SET (tisc , tisc , pd , mdev -> mlx5e_res .pdn );
3427+ MLX5_SET (tisc , tisc , pd , mdev -> mlx5e_res .hw_objs . pdn );
34283428
34293429 if (mlx5_lag_is_lacp_owner (mdev ))
34303430 MLX5_SET (tisc , tisc , strict_lag_tx_port_affinity , 1 );
@@ -3494,7 +3494,7 @@ static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
34943494static void mlx5e_build_indir_tir_ctx_common (struct mlx5e_priv * priv ,
34953495 u32 rqtn , u32 * tirc )
34963496{
3497- MLX5_SET (tirc , tirc , transport_domain , priv -> mdev -> mlx5e_res .td .tdn );
3497+ MLX5_SET (tirc , tirc , transport_domain , priv -> mdev -> mlx5e_res .hw_objs . td .tdn );
34983498 MLX5_SET (tirc , tirc , disp_type , MLX5_TIRC_DISP_TYPE_INDIRECT );
34993499 MLX5_SET (tirc , tirc , indirect_table , rqtn );
35003500 MLX5_SET (tirc , tirc , tunneled_offload_en ,
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