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Srinivas-Kandagatlabroonie
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ASoC: wcd934x: add audio routings
This patch adds audio routing for both playback and capture. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20191219103153.14875-8-srinivas.kandagatla@linaro.org Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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‎sound/soc/codecs/wcd934x.c‎

Lines changed: 290 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,162 @@
135135
} \
136136
}
137137

138+
#define WCD934X_INTERPOLATOR_PATH(id) \
139+
{"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \
140+
{"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \
141+
{"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \
142+
{"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \
143+
{"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \
144+
{"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \
145+
{"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \
146+
{"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \
147+
{"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"}, \
148+
{"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \
149+
{"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \
150+
{"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \
151+
{"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \
152+
{"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \
153+
{"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \
154+
{"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \
155+
{"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \
156+
{"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \
157+
{"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"}, \
158+
{"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \
159+
{"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \
160+
{"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \
161+
{"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \
162+
{"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \
163+
{"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \
164+
{"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \
165+
{"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \
166+
{"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \
167+
{"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"}, \
168+
{"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \
169+
{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
170+
{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
171+
{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
172+
{"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
173+
{"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
174+
{"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
175+
{"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
176+
{"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
177+
{"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
178+
{"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
179+
{"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
180+
{"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \
181+
{"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \
182+
{"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"}, \
183+
{"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"}, \
184+
{"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"}, \
185+
{"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"}, \
186+
{"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"}, \
187+
{"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"}
188+
189+
#define WCD934X_INTERPOLATOR_MIX2(id) \
190+
{"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
191+
{"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"}
192+
193+
#define WCD934X_SLIM_RX_AIF_PATH(id) \
194+
{"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"}, \
195+
{"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"}, \
196+
{"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"}, \
197+
{"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"}, \
198+
{"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"}
199+
200+
#define WCD934X_ADC_MUX(id) \
201+
{"ADC MUX" #id, "DMIC", "DMIC MUX" #id }, \
202+
{"ADC MUX" #id, "AMIC", "AMIC MUX" #id }, \
203+
{"DMIC MUX" #id, "DMIC0", "DMIC0"}, \
204+
{"DMIC MUX" #id, "DMIC1", "DMIC1"}, \
205+
{"DMIC MUX" #id, "DMIC2", "DMIC2"}, \
206+
{"DMIC MUX" #id, "DMIC3", "DMIC3"}, \
207+
{"DMIC MUX" #id, "DMIC4", "DMIC4"}, \
208+
{"DMIC MUX" #id, "DMIC5", "DMIC5"}, \
209+
{"AMIC MUX" #id, "ADC1", "ADC1"}, \
210+
{"AMIC MUX" #id, "ADC2", "ADC2"}, \
211+
{"AMIC MUX" #id, "ADC3", "ADC3"}, \
212+
{"AMIC MUX" #id, "ADC4", "ADC4"}
213+
214+
#define WCD934X_IIR_INP_MUX(id) \
215+
{"IIR" #id, NULL, "IIR" #id " INP0 MUX"}, \
216+
{"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"}, \
217+
{"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"}, \
218+
{"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"}, \
219+
{"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"}, \
220+
{"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"}, \
221+
{"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"}, \
222+
{"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"}, \
223+
{"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"}, \
224+
{"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"}, \
225+
{"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"}, \
226+
{"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"}, \
227+
{"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"}, \
228+
{"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"}, \
229+
{"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"}, \
230+
{"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"}, \
231+
{"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"}, \
232+
{"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"}, \
233+
{"IIR" #id, NULL, "IIR" #id " INP1 MUX"}, \
234+
{"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"}, \
235+
{"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"}, \
236+
{"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"}, \
237+
{"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"}, \
238+
{"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"}, \
239+
{"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"}, \
240+
{"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"}, \
241+
{"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"}, \
242+
{"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"}, \
243+
{"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"}, \
244+
{"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"}, \
245+
{"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"}, \
246+
{"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"}, \
247+
{"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"}, \
248+
{"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"}, \
249+
{"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"}, \
250+
{"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"}, \
251+
{"IIR" #id, NULL, "IIR" #id " INP2 MUX"}, \
252+
{"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"}, \
253+
{"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"}, \
254+
{"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"}, \
255+
{"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"}, \
256+
{"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"}, \
257+
{"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"}, \
258+
{"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"}, \
259+
{"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"}, \
260+
{"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"}, \
261+
{"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"}, \
262+
{"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"}, \
263+
{"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"}, \
264+
{"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"}, \
265+
{"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"}, \
266+
{"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"}, \
267+
{"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"}, \
268+
{"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"}, \
269+
{"IIR" #id, NULL, "IIR" #id " INP3 MUX"}, \
270+
{"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"}, \
271+
{"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"}, \
272+
{"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"}, \
273+
{"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"}, \
274+
{"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"}, \
275+
{"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"}, \
276+
{"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"}, \
277+
{"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"}, \
278+
{"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"}, \
279+
{"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"}, \
280+
{"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"}, \
281+
{"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"}, \
282+
{"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"}, \
283+
{"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"}, \
284+
{"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"}, \
285+
{"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"}, \
286+
{"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"}
287+
288+
#define WCD934X_SLIM_TX_AIF_PATH(id) \
289+
{"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
290+
{"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
291+
{"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
292+
{"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"}
293+
138294
enum {
139295
MIC_BIAS_1 = 1,
140296
MIC_BIAS_2,
@@ -4678,6 +4834,138 @@ static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = {
46784834
ARRAY_SIZE(aif3_slim_cap_mixer)),
46794835
};
46804836

4837+
static const struct snd_soc_dapm_route wcd934x_audio_map[] = {
4838+
/* RX0-RX7 */
4839+
WCD934X_SLIM_RX_AIF_PATH(0),
4840+
WCD934X_SLIM_RX_AIF_PATH(1),
4841+
WCD934X_SLIM_RX_AIF_PATH(2),
4842+
WCD934X_SLIM_RX_AIF_PATH(3),
4843+
WCD934X_SLIM_RX_AIF_PATH(4),
4844+
WCD934X_SLIM_RX_AIF_PATH(5),
4845+
WCD934X_SLIM_RX_AIF_PATH(6),
4846+
WCD934X_SLIM_RX_AIF_PATH(7),
4847+
4848+
/* RX0 Ear out */
4849+
WCD934X_INTERPOLATOR_PATH(0),
4850+
WCD934X_INTERPOLATOR_MIX2(0),
4851+
{"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
4852+
{"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
4853+
{"RX INT0 DAC", NULL, "RX_BIAS"},
4854+
{"EAR PA", NULL, "RX INT0 DAC"},
4855+
{"EAR", NULL, "EAR PA"},
4856+
4857+
/* RX1 Headphone left */
4858+
WCD934X_INTERPOLATOR_PATH(1),
4859+
WCD934X_INTERPOLATOR_MIX2(1),
4860+
{"RX INT1 MIX3", NULL, "RX INT1 MIX2"},
4861+
{"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"},
4862+
{"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
4863+
{"RX INT1 DAC", NULL, "RX_BIAS"},
4864+
{"HPHL PA", NULL, "RX INT1 DAC"},
4865+
{"HPHL", NULL, "HPHL PA"},
4866+
4867+
/* RX2 Headphone right */
4868+
WCD934X_INTERPOLATOR_PATH(2),
4869+
WCD934X_INTERPOLATOR_MIX2(2),
4870+
{"RX INT2 MIX3", NULL, "RX INT2 MIX2"},
4871+
{"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"},
4872+
{"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
4873+
{"RX INT2 DAC", NULL, "RX_BIAS"},
4874+
{"HPHR PA", NULL, "RX INT2 DAC"},
4875+
{"HPHR", NULL, "HPHR PA"},
4876+
4877+
/* RX3 HIFi LineOut1 */
4878+
WCD934X_INTERPOLATOR_PATH(3),
4879+
WCD934X_INTERPOLATOR_MIX2(3),
4880+
{"RX INT3 MIX3", NULL, "RX INT3 MIX2"},
4881+
{"RX INT3 DAC", NULL, "RX INT3 MIX3"},
4882+
{"RX INT3 DAC", NULL, "RX_BIAS"},
4883+
{"LINEOUT1 PA", NULL, "RX INT3 DAC"},
4884+
{"LINEOUT1", NULL, "LINEOUT1 PA"},
4885+
4886+
/* RX4 HIFi LineOut2 */
4887+
WCD934X_INTERPOLATOR_PATH(4),
4888+
WCD934X_INTERPOLATOR_MIX2(4),
4889+
{"RX INT4 MIX3", NULL, "RX INT4 MIX2"},
4890+
{"RX INT4 DAC", NULL, "RX INT4 MIX3"},
4891+
{"RX INT4 DAC", NULL, "RX_BIAS"},
4892+
{"LINEOUT2 PA", NULL, "RX INT4 DAC"},
4893+
{"LINEOUT2", NULL, "LINEOUT2 PA"},
4894+
4895+
/* RX7 Speaker Left Out PA */
4896+
WCD934X_INTERPOLATOR_PATH(7),
4897+
WCD934X_INTERPOLATOR_MIX2(7),
4898+
{"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},
4899+
{"RX INT7 CHAIN", NULL, "RX_BIAS"},
4900+
{"RX INT7 CHAIN", NULL, "SBOOST0"},
4901+
{"RX INT7 CHAIN", NULL, "SBOOST0_CLK"},
4902+
{"SPK1 OUT", NULL, "RX INT7 CHAIN"},
4903+
4904+
/* RX8 Speaker Right Out PA */
4905+
WCD934X_INTERPOLATOR_PATH(8),
4906+
{"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},
4907+
{"RX INT8 CHAIN", NULL, "RX_BIAS"},
4908+
{"RX INT8 CHAIN", NULL, "SBOOST1"},
4909+
{"RX INT8 CHAIN", NULL, "SBOOST1_CLK"},
4910+
{"SPK2 OUT", NULL, "RX INT8 CHAIN"},
4911+
4912+
/* Tx */
4913+
{"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
4914+
{"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
4915+
{"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
4916+
4917+
WCD934X_SLIM_TX_AIF_PATH(0),
4918+
WCD934X_SLIM_TX_AIF_PATH(1),
4919+
WCD934X_SLIM_TX_AIF_PATH(2),
4920+
WCD934X_SLIM_TX_AIF_PATH(3),
4921+
WCD934X_SLIM_TX_AIF_PATH(4),
4922+
WCD934X_SLIM_TX_AIF_PATH(5),
4923+
WCD934X_SLIM_TX_AIF_PATH(6),
4924+
WCD934X_SLIM_TX_AIF_PATH(7),
4925+
WCD934X_SLIM_TX_AIF_PATH(8),
4926+
4927+
WCD934X_ADC_MUX(0),
4928+
WCD934X_ADC_MUX(1),
4929+
WCD934X_ADC_MUX(2),
4930+
WCD934X_ADC_MUX(3),
4931+
WCD934X_ADC_MUX(4),
4932+
WCD934X_ADC_MUX(5),
4933+
WCD934X_ADC_MUX(6),
4934+
WCD934X_ADC_MUX(7),
4935+
WCD934X_ADC_MUX(8),
4936+
4937+
{"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},
4938+
{"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},
4939+
{"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},
4940+
{"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},
4941+
{"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},
4942+
{"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},
4943+
{"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},
4944+
{"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},
4945+
{"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},
4946+
4947+
{"AMIC4_5 SEL", "AMIC4", "AMIC4"},
4948+
{"AMIC4_5 SEL", "AMIC5", "AMIC5"},
4949+
4950+
{ "DMIC0", NULL, "DMIC0 Pin" },
4951+
{ "DMIC1", NULL, "DMIC1 Pin" },
4952+
{ "DMIC2", NULL, "DMIC2 Pin" },
4953+
{ "DMIC3", NULL, "DMIC3 Pin" },
4954+
{ "DMIC4", NULL, "DMIC4 Pin" },
4955+
{ "DMIC5", NULL, "DMIC5 Pin" },
4956+
4957+
{"ADC1", NULL, "AMIC1"},
4958+
{"ADC2", NULL, "AMIC2"},
4959+
{"ADC3", NULL, "AMIC3"},
4960+
{"ADC4", NULL, "AMIC4_5 SEL"},
4961+
4962+
WCD934X_IIR_INP_MUX(0),
4963+
WCD934X_IIR_INP_MUX(1),
4964+
4965+
{"SRC0", NULL, "IIR0"},
4966+
{"SRC1", NULL, "IIR1"},
4967+
};
4968+
46814969
static const struct snd_soc_component_driver wcd934x_component_drv = {
46824970
.probe = wcd934x_comp_probe,
46834971
.remove = wcd934x_comp_remove,
@@ -4686,6 +4974,8 @@ static const struct snd_soc_component_driver wcd934x_component_drv = {
46864974
.num_controls = ARRAY_SIZE(wcd934x_snd_controls),
46874975
.dapm_widgets = wcd934x_dapm_widgets,
46884976
.num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets),
4977+
.dapm_routes = wcd934x_audio_map,
4978+
.num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map),
46894979
};
46904980

46914981
static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd)

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