@@ -164,33 +164,46 @@ static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac)
164164 tdmac -> status = DMA_IN_PROGRESS ;
165165}
166166
167- static void mmp_tdma_disable_chan (struct mmp_tdma_chan * tdmac )
167+ static int mmp_tdma_disable_chan (struct dma_chan * chan )
168168{
169+ struct mmp_tdma_chan * tdmac = to_mmp_tdma_chan (chan );
170+
169171 writel (readl (tdmac -> reg_base + TDCR ) & ~TDCR_CHANEN ,
170172 tdmac -> reg_base + TDCR );
171173
172174 tdmac -> status = DMA_COMPLETE ;
175+
176+ return 0 ;
173177}
174178
175- static void mmp_tdma_resume_chan (struct mmp_tdma_chan * tdmac )
179+ static int mmp_tdma_resume_chan (struct dma_chan * chan )
176180{
181+ struct mmp_tdma_chan * tdmac = to_mmp_tdma_chan (chan );
182+
177183 writel (readl (tdmac -> reg_base + TDCR ) | TDCR_CHANEN ,
178184 tdmac -> reg_base + TDCR );
179185 tdmac -> status = DMA_IN_PROGRESS ;
186+
187+ return 0 ;
180188}
181189
182- static void mmp_tdma_pause_chan (struct mmp_tdma_chan * tdmac )
190+ static int mmp_tdma_pause_chan (struct dma_chan * chan )
183191{
192+ struct mmp_tdma_chan * tdmac = to_mmp_tdma_chan (chan );
193+
184194 writel (readl (tdmac -> reg_base + TDCR ) & ~TDCR_CHANEN ,
185195 tdmac -> reg_base + TDCR );
186196 tdmac -> status = DMA_PAUSED ;
197+
198+ return 0 ;
187199}
188200
189- static int mmp_tdma_config_chan (struct mmp_tdma_chan * tdmac )
201+ static int mmp_tdma_config_chan (struct dma_chan * chan )
190202{
203+ struct mmp_tdma_chan * tdmac = to_mmp_tdma_chan (chan );
191204 unsigned int tdcr = 0 ;
192205
193- mmp_tdma_disable_chan (tdmac );
206+ mmp_tdma_disable_chan (chan );
194207
195208 if (tdmac -> dir == DMA_MEM_TO_DEV )
196209 tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC ;
@@ -452,42 +465,32 @@ static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic(
452465 return NULL ;
453466}
454467
455- static int mmp_tdma_control (struct dma_chan * chan , enum dma_ctrl_cmd cmd ,
456- unsigned long arg )
468+ static int mmp_tdma_terminate_all (struct dma_chan * chan )
457469{
458470 struct mmp_tdma_chan * tdmac = to_mmp_tdma_chan (chan );
459- struct dma_slave_config * dmaengine_cfg = (void * )arg ;
460- int ret = 0 ;
461-
462- switch (cmd ) {
463- case DMA_TERMINATE_ALL :
464- mmp_tdma_disable_chan (tdmac );
465- /* disable interrupt */
466- mmp_tdma_enable_irq (tdmac , false);
467- break ;
468- case DMA_PAUSE :
469- mmp_tdma_pause_chan (tdmac );
470- break ;
471- case DMA_RESUME :
472- mmp_tdma_resume_chan (tdmac );
473- break ;
474- case DMA_SLAVE_CONFIG :
475- if (dmaengine_cfg -> direction == DMA_DEV_TO_MEM ) {
476- tdmac -> dev_addr = dmaengine_cfg -> src_addr ;
477- tdmac -> burst_sz = dmaengine_cfg -> src_maxburst ;
478- tdmac -> buswidth = dmaengine_cfg -> src_addr_width ;
479- } else {
480- tdmac -> dev_addr = dmaengine_cfg -> dst_addr ;
481- tdmac -> burst_sz = dmaengine_cfg -> dst_maxburst ;
482- tdmac -> buswidth = dmaengine_cfg -> dst_addr_width ;
483- }
484- tdmac -> dir = dmaengine_cfg -> direction ;
485- return mmp_tdma_config_chan (tdmac );
486- default :
487- ret = - ENOSYS ;
471+
472+ mmp_tdma_disable_chan (chan );
473+ /* disable interrupt */
474+ mmp_tdma_enable_irq (tdmac , false);
475+ }
476+
477+ static int mmp_tdma_config (struct dma_chan * chan ,
478+ struct dma_slave_config * dmaengine_cfg )
479+ {
480+ struct mmp_tdma_chan * tdmac = to_mmp_tdma_chan (chan );
481+
482+ if (dmaengine_cfg -> direction == DMA_DEV_TO_MEM ) {
483+ tdmac -> dev_addr = dmaengine_cfg -> src_addr ;
484+ tdmac -> burst_sz = dmaengine_cfg -> src_maxburst ;
485+ tdmac -> buswidth = dmaengine_cfg -> src_addr_width ;
486+ } else {
487+ tdmac -> dev_addr = dmaengine_cfg -> dst_addr ;
488+ tdmac -> burst_sz = dmaengine_cfg -> dst_maxburst ;
489+ tdmac -> buswidth = dmaengine_cfg -> dst_addr_width ;
488490 }
491+ tdmac -> dir = dmaengine_cfg -> direction ;
489492
490- return ret ;
493+ return mmp_tdma_config_chan ( chan ) ;
491494}
492495
493496static enum dma_status mmp_tdma_tx_status (struct dma_chan * chan ,
@@ -668,7 +671,10 @@ static int mmp_tdma_probe(struct platform_device *pdev)
668671 tdev -> device .device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic ;
669672 tdev -> device .device_tx_status = mmp_tdma_tx_status ;
670673 tdev -> device .device_issue_pending = mmp_tdma_issue_pending ;
671- tdev -> device .device_control = mmp_tdma_control ;
674+ tdev -> device .device_config = mmp_tdma_config ;
675+ tdev -> device .device_pause = mmp_tdma_pause_chan ;
676+ tdev -> device .device_resume = mmp_tdma_resume_chan ;
677+ tdev -> device .device_terminate_all = mmp_tdma_terminate_all ;
672678 tdev -> device .copy_align = TDMA_ALIGNMENT ;
673679
674680 dma_set_mask (& pdev -> dev , DMA_BIT_MASK (64 ));
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