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Danielmachonkuba-moo
Danielmachon
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kuba-moo
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net: lan969x: add RGMII registers
Configuration of RGMII is done by configuring the GPIO and clock settings in the HSIOWRAP target, and configuring the RGMII port devices in the DEVRGMII target. Both targets contain registers replicated for the number of RGMII port devices, which is two. Add said targets and register macros required to configure RGMII. Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com> Tested-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-7-fa8ba5dff732@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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‎drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -90,9 +90,12 @@ static const struct sparx5_main_io_resource lan969x_main_iomap[] = {
9090
{ TARGET_DEV2G5 + 27, 0x30d8000, 1 }, /* 0xe30d8000 */
9191
{ TARGET_DEV10G + 9, 0x30dc000, 1 }, /* 0xe30dc000 */
9292
{ TARGET_PCS10G_BR + 9, 0x30e0000, 1 }, /* 0xe30e0000 */
93+
{ TARGET_DEVRGMII, 0x30e4000, 1 }, /* 0xe30e4000 */
94+
{ TARGET_DEVRGMII + 1, 0x30e8000, 1 }, /* 0xe30e8000 */
9395
{ TARGET_DSM, 0x30ec000, 1 }, /* 0xe30ec000 */
9496
{ TARGET_PORT_CONF, 0x30f0000, 1 }, /* 0xe30f0000 */
9597
{ TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */
98+
{ TARGET_HSIO_WRAP, 0x3408000, 1 }, /* 0xe3408000 */
9699
};
97100

98101
static struct sparx5_sdlb_group lan969x_sdlb_groups[LAN969X_SDLB_GRP_CNT] = {

‎drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h‎

Lines changed: 145 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@ enum sparx5_target {
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TARGET_FDMA = 117,
3838
TARGET_GCB = 118,
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TARGET_HSCH = 119,
40+
TARGET_HSIO_WRAP = 120,
4041
TARGET_LRN = 122,
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TARGET_PCEP = 129,
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TARGET_PCS10G_BR = 132,
@@ -54,6 +55,7 @@ enum sparx5_target {
5455
TARGET_VCAP_SUPER = 326,
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TARGET_VOP = 327,
5657
TARGET_XQS = 331,
58+
TARGET_DEVRGMII = 392,
5759
NUM_TARGETS = 517
5860
};
5961

@@ -5367,6 +5369,69 @@ extern const struct sparx5_regs *regs;
53675369
#define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\
53685370
FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x)
53695371

5372+
/* LAN969X ONLY */
5373+
/* HSIOWRAP:XMII_CFG:XMII_CFG */
5374+
#define HSIO_WRAP_XMII_CFG(g) \
5375+
__REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 0, 0, 1, 4)
5376+
5377+
#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG GENMASK(2, 1)
5378+
#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_SET(x)\
5379+
FIELD_PREP(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG, x)
5380+
#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_GET(x)\
5381+
FIELD_GET(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG, x)
5382+
5383+
/* LAN969X ONLY */
5384+
/* HSIOWRAP:XMII_CFG:RGMII_CFG */
5385+
#define HSIO_WRAP_RGMII_CFG(g) \
5386+
__REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 4, 0, 1, 4)
5387+
5388+
#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG GENMASK(4, 2)
5389+
#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(x)\
5390+
FIELD_PREP(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG, x)
5391+
#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_GET(x)\
5392+
FIELD_GET(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG, x)
5393+
5394+
#define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST BIT(1)
5395+
#define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_SET(x)\
5396+
FIELD_PREP(HSIO_WRAP_RGMII_CFG_RGMII_TX_RST, x)
5397+
#define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_GET(x)\
5398+
FIELD_GET(HSIO_WRAP_RGMII_CFG_RGMII_TX_RST, x)
5399+
5400+
#define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST BIT(0)
5401+
#define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_SET(x)\
5402+
FIELD_PREP(HSIO_WRAP_RGMII_CFG_RGMII_RX_RST, x)
5403+
#define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_GET(x)\
5404+
FIELD_GET(HSIO_WRAP_RGMII_CFG_RGMII_RX_RST, x)
5405+
5406+
/* LAN969X ONLY */
5407+
/* HSIOWRAP:XMII_CFG:DLL_CFG */
5408+
#define HSIO_WRAP_DLL_CFG(g, r) \
5409+
__REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 12, r, 2, 4)
5410+
5411+
#define HSIO_WRAP_DLL_CFG_DLL_ENA BIT(19)
5412+
#define HSIO_WRAP_DLL_CFG_DLL_ENA_SET(x)\
5413+
FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_ENA, x)
5414+
#define HSIO_WRAP_DLL_CFG_DLL_ENA_GET(x)\
5415+
FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_ENA, x)
5416+
5417+
#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA BIT(18)
5418+
#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(x)\
5419+
FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_CLK_ENA, x)
5420+
#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_GET(x)\
5421+
FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_CLK_ENA, x)
5422+
5423+
#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL GENMASK(17, 15)
5424+
#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(x)\
5425+
FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, x)
5426+
#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_GET(x)\
5427+
FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, x)
5428+
5429+
#define HSIO_WRAP_DLL_CFG_DLL_RST BIT(0)
5430+
#define HSIO_WRAP_DLL_CFG_DLL_RST_SET(x)\
5431+
FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_RST, x)
5432+
#define HSIO_WRAP_DLL_CFG_DLL_RST_GET(x)\
5433+
FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_RST, x)
5434+
53705435
/* LRN:COMMON:COMMON_ACCESS_CTRL */
53715436
#define LRN_COMMON_ACCESS_CTRL \
53725437
__REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4)
@@ -8110,4 +8175,84 @@ extern const struct sparx5_regs *regs;
81108175
#define XQS_CNT(g) \
81118176
__REG(TARGET_XQS, 0, 1, 0, g, 1024, 4, 0, 0, 1, 4)
81128177

8178+
/* LAN969X ONLY */
8179+
/* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */
8180+
#define DEVRGMII_DEV_RST_CTRL(t) \
8181+
__REG(TARGET_DEVRGMII, t, 2, 0, 0, 1, 36, 0, 0, 1, 4)
8182+
8183+
#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20)
8184+
#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_SET(x)\
8185+
FIELD_PREP(DEVRGMII_DEV_RST_CTRL_SPEED_SEL, x)
8186+
#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_GET(x)\
8187+
FIELD_GET(DEVRGMII_DEV_RST_CTRL_SPEED_SEL, x)
8188+
8189+
/* LAN969X ONLY */
8190+
/* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */
8191+
#define DEVRGMII_MAC_ENA_CFG(t) \
8192+
__REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 0, 0, 1, 4)
8193+
8194+
#define DEVRGMII_MAC_ENA_CFG_RX_ENA BIT(4)
8195+
#define DEVRGMII_MAC_ENA_CFG_RX_ENA_SET(x)\
8196+
FIELD_PREP(DEVRGMII_MAC_ENA_CFG_RX_ENA, x)
8197+
#define DEVRGMII_MAC_ENA_CFG_RX_ENA_GET(x)\
8198+
FIELD_GET(DEVRGMII_MAC_ENA_CFG_RX_ENA, x)
8199+
8200+
#define DEVRGMII_MAC_ENA_CFG_TX_ENA BIT(0)
8201+
#define DEVRGMII_MAC_ENA_CFG_TX_ENA_SET(x)\
8202+
FIELD_PREP(DEVRGMII_MAC_ENA_CFG_TX_ENA, x)
8203+
#define DEVRGMII_MAC_ENA_CFG_TX_ENA_GET(x)\
8204+
FIELD_GET(DEVRGMII_MAC_ENA_CFG_TX_ENA, x)
8205+
8206+
/* LAN969X ONLY */
8207+
/* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */
8208+
#define DEVRGMII_MAC_TAGS_CFG(t) \
8209+
__REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 12, 0, 1, 4)
8210+
8211+
#define DEVRGMII_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16)
8212+
#define DEVRGMII_MAC_TAGS_CFG_TAG_ID_SET(x)\
8213+
FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_TAG_ID, x)
8214+
#define DEVRGMII_MAC_TAGS_CFG_TAG_ID_GET(x)\
8215+
FIELD_GET(DEVRGMII_MAC_TAGS_CFG_TAG_ID, x)
8216+
8217+
#define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(3)
8218+
#define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\
8219+
FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
8220+
#define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\
8221+
FIELD_GET(DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
8222+
8223+
#define DEVRGMII_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1)
8224+
#define DEVRGMII_MAC_TAGS_CFG_PB_ENA_SET(x)\
8225+
FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_PB_ENA, x)
8226+
#define DEVRGMII_MAC_TAGS_CFG_PB_ENA_GET(x)\
8227+
FIELD_GET(DEVRGMII_MAC_TAGS_CFG_PB_ENA, x)
8228+
8229+
#define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0)
8230+
#define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\
8231+
FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
8232+
#define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\
8233+
FIELD_GET(DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
8234+
8235+
/* LAN969X ONLY */
8236+
/* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */
8237+
#define DEVRGMII_MAC_IFG_CFG(t) \
8238+
__REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 24, 0, 1, 4)
8239+
8240+
#define DEVRGMII_MAC_IFG_CFG_TX_IFG GENMASK(12, 8)
8241+
#define DEVRGMII_MAC_IFG_CFG_TX_IFG_SET(x)\
8242+
FIELD_PREP(DEVRGMII_MAC_IFG_CFG_TX_IFG, x)
8243+
#define DEVRGMII_MAC_IFG_CFG_TX_IFG_GET(x)\
8244+
FIELD_GET(DEVRGMII_MAC_IFG_CFG_TX_IFG, x)
8245+
8246+
#define DEVRGMII_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4)
8247+
#define DEVRGMII_MAC_IFG_CFG_RX_IFG2_SET(x)\
8248+
FIELD_PREP(DEVRGMII_MAC_IFG_CFG_RX_IFG2, x)
8249+
#define DEVRGMII_MAC_IFG_CFG_RX_IFG2_GET(x)\
8250+
FIELD_GET(DEVRGMII_MAC_IFG_CFG_RX_IFG2, x)
8251+
8252+
#define DEVRGMII_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0)
8253+
#define DEVRGMII_MAC_IFG_CFG_RX_IFG1_SET(x)\
8254+
FIELD_PREP(DEVRGMII_MAC_IFG_CFG_RX_IFG1, x)
8255+
#define DEVRGMII_MAC_IFG_CFG_RX_IFG1_GET(x)\
8256+
FIELD_GET(DEVRGMII_MAC_IFG_CFG_RX_IFG1, x)
8257+
81138258
#endif /* _SPARX5_MAIN_REGS_H_ */

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